1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/io/io_block.h> 14 #include <drivers/io/io_driver.h> 15 #include <drivers/io/io_fip.h> 16 #include <drivers/io/io_memmap.h> 17 #include <drivers/io/io_mtd.h> 18 #include <drivers/io/io_storage.h> 19 #include <drivers/mmc.h> 20 #include <drivers/partition/partition.h> 21 #include <drivers/raw_nand.h> 22 #include <drivers/spi_nand.h> 23 #include <drivers/spi_nor.h> 24 #include <drivers/st/io_mmc.h> 25 #include <drivers/st/stm32_fmc2_nand.h> 26 #include <drivers/st/stm32_qspi.h> 27 #include <drivers/st/stm32_sdmmc2.h> 28 #include <drivers/usb_device.h> 29 #include <lib/fconf/fconf.h> 30 #include <lib/mmio.h> 31 #include <lib/utils.h> 32 #include <plat/common/platform.h> 33 #include <tools_share/firmware_image_package.h> 34 35 #include <platform_def.h> 36 #include <stm32cubeprogrammer.h> 37 #include <stm32mp_fconf_getter.h> 38 #include <usb_dfu.h> 39 40 /* IO devices */ 41 uintptr_t fip_dev_handle; 42 uintptr_t storage_dev_handle; 43 44 static const io_dev_connector_t *fip_dev_con; 45 46 #if STM32MP_SDMMC || STM32MP_EMMC 47 static struct mmc_device_info mmc_info; 48 49 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 50 51 static io_block_dev_spec_t mmc_block_dev_spec = { 52 /* It's used as temp buffer in block driver */ 53 .buffer = { 54 .offset = (size_t)&block_buffer, 55 .length = MMC_BLOCK_SIZE, 56 }, 57 .ops = { 58 .read = mmc_read_blocks, 59 .write = NULL, 60 }, 61 .block_size = MMC_BLOCK_SIZE, 62 }; 63 64 static const io_dev_connector_t *mmc_dev_con; 65 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 66 67 #if STM32MP_SPI_NOR 68 static io_mtd_dev_spec_t spi_nor_dev_spec = { 69 .ops = { 70 .init = spi_nor_init, 71 .read = spi_nor_read, 72 }, 73 }; 74 #endif 75 76 #if STM32MP_RAW_NAND 77 static io_mtd_dev_spec_t nand_dev_spec = { 78 .ops = { 79 .init = nand_raw_init, 80 .read = nand_read, 81 .seek = nand_seek_bb 82 }, 83 }; 84 85 static const io_dev_connector_t *nand_dev_con; 86 #endif 87 88 #if STM32MP_SPI_NAND 89 static io_mtd_dev_spec_t spi_nand_dev_spec = { 90 .ops = { 91 .init = spi_nand_init, 92 .read = nand_read, 93 .seek = nand_seek_bb 94 }, 95 }; 96 #endif 97 98 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 99 static const io_dev_connector_t *spi_dev_con; 100 #endif 101 102 #if STM32MP_USB_PROGRAMMER 103 static const io_dev_connector_t *memmap_dev_con; 104 #endif 105 106 io_block_spec_t image_block_spec = { 107 .offset = 0U, 108 .length = 0U, 109 }; 110 111 int open_fip(const uintptr_t spec) 112 { 113 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); 114 } 115 116 int open_storage(const uintptr_t spec) 117 { 118 return io_dev_init(storage_dev_handle, 0); 119 } 120 121 static void print_boot_device(boot_api_context_t *boot_context) 122 { 123 switch (boot_context->boot_interface_selected) { 124 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 125 INFO("Using SDMMC\n"); 126 break; 127 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 128 INFO("Using EMMC\n"); 129 break; 130 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 131 INFO("Using QSPI NOR\n"); 132 break; 133 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 134 INFO("Using FMC NAND\n"); 135 break; 136 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 137 INFO("Using SPI NAND\n"); 138 break; 139 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 140 INFO("Using USB\n"); 141 break; 142 default: 143 ERROR("Boot interface %u not found\n", 144 boot_context->boot_interface_selected); 145 panic(); 146 break; 147 } 148 149 if (boot_context->boot_interface_instance != 0U) { 150 INFO(" Instance %d\n", boot_context->boot_interface_instance); 151 } 152 } 153 154 #if STM32MP_SDMMC || STM32MP_EMMC 155 static void boot_mmc(enum mmc_device_type mmc_dev_type, 156 uint16_t boot_interface_instance) 157 { 158 int io_result __unused; 159 struct stm32_sdmmc2_params params; 160 161 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 162 163 mmc_info.mmc_dev_type = mmc_dev_type; 164 165 switch (boot_interface_instance) { 166 case 1: 167 params.reg_base = STM32MP_SDMMC1_BASE; 168 break; 169 case 2: 170 params.reg_base = STM32MP_SDMMC2_BASE; 171 break; 172 case 3: 173 params.reg_base = STM32MP_SDMMC3_BASE; 174 break; 175 default: 176 WARN("SDMMC instance not found, using default\n"); 177 if (mmc_dev_type == MMC_IS_SD) { 178 params.reg_base = STM32MP_SDMMC1_BASE; 179 } else { 180 params.reg_base = STM32MP_SDMMC2_BASE; 181 } 182 break; 183 } 184 185 params.device_info = &mmc_info; 186 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 187 ERROR("SDMMC%u init failed\n", boot_interface_instance); 188 panic(); 189 } 190 191 /* Open MMC as a block device to read GPT table */ 192 io_result = register_io_dev_block(&mmc_dev_con); 193 if (io_result != 0) { 194 panic(); 195 } 196 197 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 198 &storage_dev_handle); 199 assert(io_result == 0); 200 } 201 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 202 203 #if STM32MP_SPI_NOR 204 static void boot_spi_nor(boot_api_context_t *boot_context) 205 { 206 int io_result __unused; 207 208 io_result = stm32_qspi_init(); 209 assert(io_result == 0); 210 211 io_result = register_io_dev_mtd(&spi_dev_con); 212 assert(io_result == 0); 213 214 /* Open connections to device */ 215 io_result = io_dev_open(spi_dev_con, 216 (uintptr_t)&spi_nor_dev_spec, 217 &storage_dev_handle); 218 assert(io_result == 0); 219 } 220 #endif /* STM32MP_SPI_NOR */ 221 222 #if STM32MP_RAW_NAND 223 static void boot_fmc2_nand(boot_api_context_t *boot_context) 224 { 225 int io_result __unused; 226 227 io_result = stm32_fmc2_init(); 228 assert(io_result == 0); 229 230 /* Register the IO device on this platform */ 231 io_result = register_io_dev_mtd(&nand_dev_con); 232 assert(io_result == 0); 233 234 /* Open connections to device */ 235 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 236 &storage_dev_handle); 237 assert(io_result == 0); 238 } 239 #endif /* STM32MP_RAW_NAND */ 240 241 #if STM32MP_SPI_NAND 242 static void boot_spi_nand(boot_api_context_t *boot_context) 243 { 244 int io_result __unused; 245 246 io_result = stm32_qspi_init(); 247 assert(io_result == 0); 248 249 io_result = register_io_dev_mtd(&spi_dev_con); 250 assert(io_result == 0); 251 252 /* Open connections to device */ 253 io_result = io_dev_open(spi_dev_con, 254 (uintptr_t)&spi_nand_dev_spec, 255 &storage_dev_handle); 256 assert(io_result == 0); 257 } 258 #endif /* STM32MP_SPI_NAND */ 259 260 #if STM32MP_USB_PROGRAMMER 261 static void mmap_io_setup(void) 262 { 263 int io_result __unused; 264 265 io_result = register_io_dev_memmap(&memmap_dev_con); 266 assert(io_result == 0); 267 268 io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, 269 &storage_dev_handle); 270 assert(io_result == 0); 271 } 272 273 static void stm32cubeprogrammer_usb(void) 274 { 275 int ret __unused; 276 struct usb_handle *pdev; 277 278 /* Init USB on platform */ 279 pdev = usb_dfu_plat_init(); 280 281 ret = stm32cubeprog_usb_load(pdev, DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 282 assert(ret == 0); 283 } 284 #endif 285 286 void stm32mp_io_setup(void) 287 { 288 int io_result __unused; 289 boot_api_context_t *boot_context = 290 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 291 292 print_boot_device(boot_context); 293 294 if ((boot_context->boot_partition_used_toboot == 1U) || 295 (boot_context->boot_partition_used_toboot == 2U)) { 296 INFO("Boot used partition fsbl%u\n", 297 boot_context->boot_partition_used_toboot); 298 } 299 300 io_result = register_io_dev_fip(&fip_dev_con); 301 assert(io_result == 0); 302 303 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, 304 &fip_dev_handle); 305 306 switch (boot_context->boot_interface_selected) { 307 #if STM32MP_SDMMC 308 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 309 dmbsy(); 310 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 311 break; 312 #endif 313 #if STM32MP_EMMC 314 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 315 dmbsy(); 316 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 317 break; 318 #endif 319 #if STM32MP_SPI_NOR 320 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 321 dmbsy(); 322 boot_spi_nor(boot_context); 323 break; 324 #endif 325 #if STM32MP_RAW_NAND 326 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 327 dmbsy(); 328 boot_fmc2_nand(boot_context); 329 break; 330 #endif 331 #if STM32MP_SPI_NAND 332 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 333 dmbsy(); 334 boot_spi_nand(boot_context); 335 break; 336 #endif 337 #if STM32MP_USB_PROGRAMMER 338 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 339 dmbsy(); 340 mmap_io_setup(); 341 break; 342 #endif 343 344 default: 345 ERROR("Boot interface %d not supported\n", 346 boot_context->boot_interface_selected); 347 panic(); 348 break; 349 } 350 } 351 352 int bl2_plat_handle_pre_image_load(unsigned int image_id) 353 { 354 static bool gpt_init_done __unused; 355 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 356 357 switch (boot_itf) { 358 #if STM32MP_SDMMC || STM32MP_EMMC 359 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 360 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 361 if (!gpt_init_done) { 362 const partition_entry_t *entry; 363 364 partition_init(GPT_IMAGE_ID); 365 entry = get_partition_entry(FIP_IMAGE_NAME); 366 if (entry == NULL) { 367 ERROR("Could NOT find the %s partition!\n", 368 FIP_IMAGE_NAME); 369 return -ENOENT; 370 } 371 372 image_block_spec.offset = entry->start; 373 image_block_spec.length = entry->length; 374 375 gpt_init_done = true; 376 } else { 377 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 378 379 mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base; 380 mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size; 381 } 382 383 break; 384 #endif 385 386 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 387 #if STM32MP_RAW_NAND 388 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 389 #endif 390 #if STM32MP_SPI_NAND 391 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 392 #endif 393 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET; 394 break; 395 #endif 396 397 #if STM32MP_SPI_NOR 398 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 399 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET; 400 break; 401 #endif 402 403 #if STM32MP_USB_PROGRAMMER 404 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 405 if (image_id == FW_CONFIG_ID) { 406 stm32cubeprogrammer_usb(); 407 /* FIP loaded at DWL address */ 408 image_block_spec.offset = DWL_BUFFER_BASE; 409 image_block_spec.length = DWL_BUFFER_SIZE; 410 } 411 break; 412 #endif 413 414 default: 415 ERROR("FIP Not found\n"); 416 panic(); 417 } 418 419 return 0; 420 } 421 422 /* 423 * Return an IO device handle and specification which can be used to access 424 * an image. Use this to enforce platform load policy. 425 */ 426 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 427 uintptr_t *image_spec) 428 { 429 int rc; 430 const struct plat_io_policy *policy; 431 432 policy = FCONF_GET_PROPERTY(stm32mp, io_policies, image_id); 433 rc = policy->check(policy->image_spec); 434 if (rc == 0) { 435 *image_spec = policy->image_spec; 436 *dev_handle = *(policy->dev_handle); 437 } 438 439 return rc; 440 } 441