1 /* 2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <arch_helpers.h> 14 #include <arch_features.h> 15 #include <bl31/bl31.h> 16 #include <common/debug.h> 17 #include <common/runtime_svc.h> 18 #include <context.h> 19 #include <lib/el3_runtime/context_mgmt.h> 20 #include <lib/el3_runtime/pubsub.h> 21 #include <lib/gpt_rme/gpt_rme.h> 22 23 #include <lib/spinlock.h> 24 #include <lib/utils.h> 25 #include <lib/xlat_tables/xlat_tables_v2.h> 26 #include <plat/common/common_def.h> 27 #include <plat/common/platform.h> 28 #include <platform_def.h> 29 #include <services/rmmd_svc.h> 30 #include <smccc_helpers.h> 31 #include <lib/extensions/sve.h> 32 #include "rmmd_initial_context.h" 33 #include "rmmd_private.h" 34 35 /******************************************************************************* 36 * RMM context information. 37 ******************************************************************************/ 38 rmmd_rmm_context_t rmm_context[PLATFORM_CORE_COUNT]; 39 40 /******************************************************************************* 41 * RMM entry point information. Discovered on the primary core and reused 42 * on secondary cores. 43 ******************************************************************************/ 44 static entry_point_info_t *rmm_ep_info; 45 46 /******************************************************************************* 47 * Static function declaration. 48 ******************************************************************************/ 49 static int32_t rmm_init(void); 50 51 /******************************************************************************* 52 * This function takes an RMM context pointer and performs a synchronous entry 53 * into it. 54 ******************************************************************************/ 55 uint64_t rmmd_rmm_sync_entry(rmmd_rmm_context_t *rmm_ctx) 56 { 57 uint64_t rc; 58 59 assert(rmm_ctx != NULL); 60 61 cm_set_context(&(rmm_ctx->cpu_ctx), REALM); 62 63 /* Restore the realm context assigned above */ 64 cm_el1_sysregs_context_restore(REALM); 65 cm_el2_sysregs_context_restore(REALM); 66 cm_set_next_eret_context(REALM); 67 68 /* Enter RMM */ 69 rc = rmmd_rmm_enter(&rmm_ctx->c_rt_ctx); 70 71 /* 72 * Save realm context. EL1 and EL2 Non-secure 73 * contexts will be restored before exiting to 74 * Non-secure world, therefore there is no need 75 * to clear EL1 and EL2 context registers. 76 */ 77 cm_el1_sysregs_context_save(REALM); 78 cm_el2_sysregs_context_save(REALM); 79 80 return rc; 81 } 82 83 /******************************************************************************* 84 * This function returns to the place where rmmd_rmm_sync_entry() was 85 * called originally. 86 ******************************************************************************/ 87 __dead2 void rmmd_rmm_sync_exit(uint64_t rc) 88 { 89 rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()]; 90 91 /* Get context of the RMM in use by this CPU. */ 92 assert(cm_get_context(REALM) == &(ctx->cpu_ctx)); 93 94 /* 95 * The RMMD must have initiated the original request through a 96 * synchronous entry into RMM. Jump back to the original C runtime 97 * context with the value of rc in x0; 98 */ 99 rmmd_rmm_exit(ctx->c_rt_ctx, rc); 100 101 panic(); 102 } 103 104 static void rmm_el2_context_init(el2_sysregs_t *regs) 105 { 106 regs->ctx_regs[CTX_SPSR_EL2 >> 3] = REALM_SPSR_EL2; 107 regs->ctx_regs[CTX_SCTLR_EL2 >> 3] = SCTLR_EL2_RES1; 108 } 109 110 /******************************************************************************* 111 * Enable architecture extensions on first entry to Realm world. 112 ******************************************************************************/ 113 static void manage_extensions_realm(cpu_context_t *ctx) 114 { 115 #if ENABLE_SVE_FOR_NS 116 /* 117 * Enable SVE and FPU in realm context when it is enabled for NS. 118 * Realm manager must ensure that the SVE and FPU register 119 * contexts are properly managed. 120 */ 121 sve_enable(ctx); 122 #else 123 /* 124 * Disable SVE and FPU in realm context when it is disabled for NS. 125 */ 126 sve_disable(ctx); 127 #endif /* ENABLE_SVE_FOR_NS */ 128 } 129 130 /******************************************************************************* 131 * Jump to the RMM for the first time. 132 ******************************************************************************/ 133 static int32_t rmm_init(void) 134 { 135 136 uint64_t rc; 137 138 rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()]; 139 140 INFO("RMM init start.\n"); 141 ctx->state = RMM_STATE_RESET; 142 143 /* Enable architecture extensions */ 144 manage_extensions_realm(&ctx->cpu_ctx); 145 146 /* Initialize RMM EL2 context. */ 147 rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx); 148 149 rc = rmmd_rmm_sync_entry(ctx); 150 if (rc != 0ULL) { 151 ERROR("RMM initialisation failed 0x%" PRIx64 "\n", rc); 152 panic(); 153 } 154 155 ctx->state = RMM_STATE_IDLE; 156 INFO("RMM init end.\n"); 157 158 return 1; 159 } 160 161 /******************************************************************************* 162 * Load and read RMM manifest, setup RMM. 163 ******************************************************************************/ 164 int rmmd_setup(void) 165 { 166 uint32_t ep_attr; 167 unsigned int linear_id = plat_my_core_pos(); 168 rmmd_rmm_context_t *rmm_ctx = &rmm_context[linear_id]; 169 170 /* Make sure RME is supported. */ 171 assert(get_armv9_2_feat_rme_support() != 0U); 172 173 rmm_ep_info = bl31_plat_get_next_image_ep_info(REALM); 174 if (rmm_ep_info == NULL) { 175 WARN("No RMM image provided by BL2 boot loader, Booting " 176 "device without RMM initialization. SMCs destined for " 177 "RMM will return SMC_UNK\n"); 178 return -ENOENT; 179 } 180 181 /* Under no circumstances will this parameter be 0 */ 182 assert(rmm_ep_info->pc == RMM_BASE); 183 184 /* Initialise an entrypoint to set up the CPU context */ 185 ep_attr = EP_REALM; 186 if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0U) { 187 ep_attr |= EP_EE_BIG; 188 } 189 190 SET_PARAM_HEAD(rmm_ep_info, PARAM_EP, VERSION_1, ep_attr); 191 rmm_ep_info->spsr = SPSR_64(MODE_EL2, 192 MODE_SP_ELX, 193 DISABLE_ALL_EXCEPTIONS); 194 195 /* Initialise RMM context with this entry point information */ 196 cm_setup_context(&rmm_ctx->cpu_ctx, rmm_ep_info); 197 198 INFO("RMM setup done.\n"); 199 200 /* Register init function for deferred init. */ 201 bl31_register_rmm_init(&rmm_init); 202 203 return 0; 204 } 205 206 /******************************************************************************* 207 * Forward SMC to the other security state 208 ******************************************************************************/ 209 static uint64_t rmmd_smc_forward(uint32_t src_sec_state, 210 uint32_t dst_sec_state, uint64_t x0, 211 uint64_t x1, uint64_t x2, uint64_t x3, 212 uint64_t x4, void *handle) 213 { 214 /* Save incoming security state */ 215 cm_el1_sysregs_context_save(src_sec_state); 216 cm_el2_sysregs_context_save(src_sec_state); 217 218 /* Restore outgoing security state */ 219 cm_el1_sysregs_context_restore(dst_sec_state); 220 cm_el2_sysregs_context_restore(dst_sec_state); 221 cm_set_next_eret_context(dst_sec_state); 222 223 /* 224 * As per SMCCCv1.1, we need to preserve x4 to x7 unless 225 * being used as return args. Hence we differentiate the 226 * onward and backward path. Support upto 8 args in the 227 * onward path and 4 args in return path. 228 */ 229 if (src_sec_state == NON_SECURE) { 230 SMC_RET8(cm_get_context(dst_sec_state), x0, x1, x2, x3, x4, 231 SMC_GET_GP(handle, CTX_GPREG_X5), 232 SMC_GET_GP(handle, CTX_GPREG_X6), 233 SMC_GET_GP(handle, CTX_GPREG_X7)); 234 } else { 235 SMC_RET4(cm_get_context(dst_sec_state), x0, x1, x2, x3); 236 } 237 } 238 239 /******************************************************************************* 240 * This function handles all SMCs in the range reserved for RMI. Each call is 241 * either forwarded to the other security state or handled by the RMM dispatcher 242 ******************************************************************************/ 243 uint64_t rmmd_rmi_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, 244 uint64_t x3, uint64_t x4, void *cookie, 245 void *handle, uint64_t flags) 246 { 247 rmmd_rmm_context_t *ctx = &rmm_context[plat_my_core_pos()]; 248 uint32_t src_sec_state; 249 250 /* Determine which security state this SMC originated from */ 251 src_sec_state = caller_sec_state(flags); 252 253 /* RMI must not be invoked by the Secure world */ 254 if (src_sec_state == SMC_FROM_SECURE) { 255 WARN("RMMD: RMI invoked by secure world.\n"); 256 SMC_RET1(handle, SMC_UNK); 257 } 258 259 /* 260 * Forward an RMI call from the Normal world to the Realm world as it 261 * is. 262 */ 263 if (src_sec_state == SMC_FROM_NON_SECURE) { 264 VERBOSE("RMMD: RMI call from non-secure world.\n"); 265 return rmmd_smc_forward(NON_SECURE, REALM, smc_fid, 266 x1, x2, x3, x4, handle); 267 } 268 269 if (src_sec_state != SMC_FROM_REALM) { 270 SMC_RET1(handle, SMC_UNK); 271 } 272 273 switch (smc_fid) { 274 case RMMD_RMI_REQ_COMPLETE: 275 if (ctx->state == RMM_STATE_RESET) { 276 VERBOSE("RMMD: running rmmd_rmm_sync_exit\n"); 277 rmmd_rmm_sync_exit(x1); 278 } 279 280 return rmmd_smc_forward(REALM, NON_SECURE, x1, 281 x2, x3, x4, 0, handle); 282 283 default: 284 WARN("RMMD: Unsupported RMM call 0x%08x\n", smc_fid); 285 SMC_RET1(handle, SMC_UNK); 286 } 287 } 288 289 /******************************************************************************* 290 * This cpu has been turned on. Enter RMM to initialise R-EL2. Entry into RMM 291 * is done after initialising minimal architectural state that guarantees safe 292 * execution. 293 ******************************************************************************/ 294 static void *rmmd_cpu_on_finish_handler(const void *arg) 295 { 296 int32_t rc; 297 uint32_t linear_id = plat_my_core_pos(); 298 rmmd_rmm_context_t *ctx = &rmm_context[linear_id]; 299 300 ctx->state = RMM_STATE_RESET; 301 302 /* Initialise RMM context with this entry point information */ 303 cm_setup_context(&ctx->cpu_ctx, rmm_ep_info); 304 305 /* Enable architecture extensions */ 306 manage_extensions_realm(&ctx->cpu_ctx); 307 308 /* Initialize RMM EL2 context. */ 309 rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx); 310 311 rc = rmmd_rmm_sync_entry(ctx); 312 if (rc != 0) { 313 ERROR("RMM initialisation failed (%d) on CPU%d\n", rc, 314 linear_id); 315 panic(); 316 } 317 318 ctx->state = RMM_STATE_IDLE; 319 return NULL; 320 } 321 322 /* Subscribe to PSCI CPU on to initialize RMM on secondary */ 323 SUBSCRIBE_TO_EVENT(psci_cpu_on_finish, rmmd_cpu_on_finish_handler); 324 325 /* Convert GPT lib error to RMMD GTS error */ 326 static int gpt_to_gts_error(int error, uint32_t smc_fid, uint64_t address) 327 { 328 int ret; 329 330 if (error == 0) { 331 return RMMD_OK; 332 } 333 334 if (error == -EINVAL) { 335 ret = RMMD_ERR_BAD_ADDR; 336 } else { 337 /* This is the only other error code we expect */ 338 assert(error == -EPERM); 339 ret = RMMD_ERR_BAD_PAS; 340 } 341 342 ERROR("RMMD: PAS Transition failed. GPT ret = %d, PA: 0x%"PRIx64 ", FID = 0x%x\n", 343 error, address, smc_fid); 344 return ret; 345 } 346 347 /******************************************************************************* 348 * This function handles RMM-EL3 interface SMCs 349 ******************************************************************************/ 350 uint64_t rmmd_rmm_el3_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, 351 uint64_t x3, uint64_t x4, void *cookie, 352 void *handle, uint64_t flags) 353 { 354 uint32_t src_sec_state; 355 int ret; 356 357 /* Determine which security state this SMC originated from */ 358 src_sec_state = caller_sec_state(flags); 359 360 if (src_sec_state != SMC_FROM_REALM) { 361 WARN("RMMD: RMM-EL3 call originated from secure or normal world\n"); 362 SMC_RET1(handle, SMC_UNK); 363 } 364 365 switch (smc_fid) { 366 case RMMD_GTSI_DELEGATE: 367 ret = gpt_delegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM); 368 SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1)); 369 case RMMD_GTSI_UNDELEGATE: 370 ret = gpt_undelegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM); 371 SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1)); 372 case RMMD_ATTEST_GET_PLAT_TOKEN: 373 ret = rmmd_attest_get_platform_token(x1, &x2, x3); 374 SMC_RET2(handle, ret, x2); 375 case RMMD_ATTEST_GET_REALM_KEY: 376 ret = rmmd_attest_get_signing_key(x1, &x2, x3); 377 SMC_RET2(handle, ret, x2); 378 default: 379 WARN("RMMD: Unsupported RMM-EL3 call 0x%08x\n", smc_fid); 380 SMC_RET1(handle, SMC_UNK); 381 } 382 } 383