1 /* 2 * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/clk.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/stm32_gpio.h> 18 #include <drivers/st/stm32_sdmmc2.h> 19 #include <drivers/st/stm32mp_reset.h> 20 #include <lib/mmio.h> 21 #include <lib/utils.h> 22 #include <libfdt.h> 23 #include <plat/common/platform.h> 24 25 #include <platform_def.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_PWRCTRL_PWR_CYCLE BIT(1) 54 #define SDMMC_POWER_DIRPOL BIT(4) 55 56 /* SDMMC clock control register */ 57 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 58 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 59 #define SDMMC_CLKCR_NEGEDGE BIT(16) 60 #define SDMMC_CLKCR_HWFC_EN BIT(17) 61 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 62 63 /* SDMMC command register */ 64 #define SDMMC_CMDR_CMDTRANS BIT(6) 65 #define SDMMC_CMDR_CMDSTOP BIT(7) 66 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 67 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 68 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 69 #define SDMMC_CMDR_CPSMEN BIT(12) 70 71 /* SDMMC data control register */ 72 #define SDMMC_DCTRLR_DTEN BIT(0) 73 #define SDMMC_DCTRLR_DTDIR BIT(1) 74 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 75 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4 77 #define SDMMC_DCTRLR_FIFORST BIT(13) 78 79 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 80 SDMMC_DCTRLR_DTDIR | \ 81 SDMMC_DCTRLR_DTMODE | \ 82 SDMMC_DCTRLR_DBLOCKSIZE) 83 84 /* SDMMC status register */ 85 #define SDMMC_STAR_CCRCFAIL BIT(0) 86 #define SDMMC_STAR_DCRCFAIL BIT(1) 87 #define SDMMC_STAR_CTIMEOUT BIT(2) 88 #define SDMMC_STAR_DTIMEOUT BIT(3) 89 #define SDMMC_STAR_TXUNDERR BIT(4) 90 #define SDMMC_STAR_RXOVERR BIT(5) 91 #define SDMMC_STAR_CMDREND BIT(6) 92 #define SDMMC_STAR_CMDSENT BIT(7) 93 #define SDMMC_STAR_DATAEND BIT(8) 94 #define SDMMC_STAR_DBCKEND BIT(10) 95 #define SDMMC_STAR_DPSMACT BIT(12) 96 #define SDMMC_STAR_RXFIFOHF BIT(15) 97 #define SDMMC_STAR_RXFIFOE BIT(19) 98 #define SDMMC_STAR_IDMATE BIT(27) 99 #define SDMMC_STAR_IDMABTC BIT(28) 100 101 /* SDMMC DMA control register */ 102 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 103 104 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 105 SDMMC_STAR_DCRCFAIL | \ 106 SDMMC_STAR_CTIMEOUT | \ 107 SDMMC_STAR_DTIMEOUT | \ 108 SDMMC_STAR_TXUNDERR | \ 109 SDMMC_STAR_RXOVERR | \ 110 SDMMC_STAR_CMDREND | \ 111 SDMMC_STAR_CMDSENT | \ 112 SDMMC_STAR_DATAEND | \ 113 SDMMC_STAR_DBCKEND | \ 114 SDMMC_STAR_IDMATE | \ 115 SDMMC_STAR_IDMABTC) 116 117 #define TIMEOUT_US_1_MS 1000U 118 #define TIMEOUT_US_10_MS 10000U 119 #define TIMEOUT_US_1_S 1000000U 120 121 /* Power cycle delays in ms */ 122 #define VCC_POWER_OFF_DELAY 2 123 #define VCC_POWER_ON_DELAY 2 124 #define POWER_CYCLE_DELAY 2 125 #define POWER_OFF_DELAY 2 126 #define POWER_ON_DELAY 1 127 128 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 129 130 static void stm32_sdmmc2_init(void); 131 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 132 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 133 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 134 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 135 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 136 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 137 138 static const struct mmc_ops stm32_sdmmc2_ops = { 139 .init = stm32_sdmmc2_init, 140 .send_cmd = stm32_sdmmc2_send_cmd, 141 .set_ios = stm32_sdmmc2_set_ios, 142 .prepare = stm32_sdmmc2_prepare, 143 .read = stm32_sdmmc2_read, 144 .write = stm32_sdmmc2_write, 145 }; 146 147 static struct stm32_sdmmc2_params sdmmc2_params; 148 149 #pragma weak plat_sdmmc2_use_dma 150 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 151 { 152 return false; 153 } 154 155 static void stm32_sdmmc2_init(void) 156 { 157 uint32_t clock_div; 158 uint32_t freq = STM32MP_MMC_INIT_FREQ; 159 uintptr_t base = sdmmc2_params.reg_base; 160 int ret; 161 162 if (sdmmc2_params.max_freq != 0U) { 163 freq = MIN(sdmmc2_params.max_freq, freq); 164 } 165 166 if (sdmmc2_params.vmmc_regu != NULL) { 167 ret = regulator_disable(sdmmc2_params.vmmc_regu); 168 if (ret < 0) { 169 panic(); 170 } 171 } 172 173 mdelay(VCC_POWER_OFF_DELAY); 174 175 mmio_write_32(base + SDMMC_POWER, 176 SDMMC_POWER_PWRCTRL_PWR_CYCLE | sdmmc2_params.dirpol); 177 mdelay(POWER_CYCLE_DELAY); 178 179 if (sdmmc2_params.vmmc_regu != NULL) { 180 ret = regulator_enable(sdmmc2_params.vmmc_regu); 181 if (ret < 0) { 182 panic(); 183 } 184 } 185 186 mdelay(VCC_POWER_ON_DELAY); 187 188 mmio_write_32(base + SDMMC_POWER, sdmmc2_params.dirpol); 189 mdelay(POWER_OFF_DELAY); 190 191 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); 192 193 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 194 sdmmc2_params.negedge | 195 sdmmc2_params.pin_ckin); 196 197 mmio_write_32(base + SDMMC_POWER, 198 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 199 200 mdelay(POWER_ON_DELAY); 201 } 202 203 static int stm32_sdmmc2_stop_transfer(void) 204 { 205 struct mmc_cmd cmd_stop; 206 207 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 208 209 cmd_stop.cmd_idx = MMC_CMD(12); 210 cmd_stop.resp_type = MMC_RESPONSE_R1B; 211 212 return stm32_sdmmc2_send_cmd(&cmd_stop); 213 } 214 215 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 216 { 217 uint64_t timeout; 218 uint32_t flags_cmd, status; 219 uint32_t flags_data = 0; 220 int err = 0; 221 uintptr_t base = sdmmc2_params.reg_base; 222 unsigned int cmd_reg, arg_reg; 223 224 if (cmd == NULL) { 225 return -EINVAL; 226 } 227 228 flags_cmd = SDMMC_STAR_CTIMEOUT; 229 arg_reg = cmd->cmd_arg; 230 231 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 232 mmio_write_32(base + SDMMC_CMDR, 0); 233 } 234 235 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 236 237 if (cmd->resp_type == 0U) { 238 flags_cmd |= SDMMC_STAR_CMDSENT; 239 } 240 241 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 242 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 243 flags_cmd |= SDMMC_STAR_CMDREND; 244 cmd_reg |= SDMMC_CMDR_WAITRESP; 245 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 246 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 247 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 248 } else { 249 flags_cmd |= SDMMC_STAR_CMDREND; 250 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 251 } 252 } 253 254 switch (cmd->cmd_idx) { 255 case MMC_CMD(1): 256 arg_reg |= OCR_POWERUP; 257 break; 258 case MMC_CMD(8): 259 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 260 cmd_reg |= SDMMC_CMDR_CMDTRANS; 261 } 262 break; 263 case MMC_CMD(12): 264 cmd_reg |= SDMMC_CMDR_CMDSTOP; 265 break; 266 case MMC_CMD(17): 267 case MMC_CMD(18): 268 cmd_reg |= SDMMC_CMDR_CMDTRANS; 269 if (sdmmc2_params.use_dma) { 270 flags_data |= SDMMC_STAR_DCRCFAIL | 271 SDMMC_STAR_DTIMEOUT | 272 SDMMC_STAR_DATAEND | 273 SDMMC_STAR_RXOVERR | 274 SDMMC_STAR_IDMATE; 275 } 276 break; 277 case MMC_ACMD(41): 278 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 279 break; 280 case MMC_ACMD(51): 281 cmd_reg |= SDMMC_CMDR_CMDTRANS; 282 if (sdmmc2_params.use_dma) { 283 flags_data |= SDMMC_STAR_DCRCFAIL | 284 SDMMC_STAR_DTIMEOUT | 285 SDMMC_STAR_DATAEND | 286 SDMMC_STAR_RXOVERR | 287 SDMMC_STAR_IDMATE | 288 SDMMC_STAR_DBCKEND; 289 } 290 break; 291 default: 292 break; 293 } 294 295 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 296 297 /* 298 * Clear the SDMMC_DCTRLR if the command does not await data. 299 * Skip CMD55 as the next command could be data related, and 300 * the register could have been set in prepare function. 301 */ 302 if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) && 303 (cmd->cmd_idx != MMC_CMD(55))) { 304 mmio_write_32(base + SDMMC_DCTRLR, 0U); 305 } 306 307 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 308 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 309 } 310 311 mmio_write_32(base + SDMMC_ARGR, arg_reg); 312 313 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 314 315 status = mmio_read_32(base + SDMMC_STAR); 316 317 timeout = timeout_init_us(TIMEOUT_US_10_MS); 318 319 while ((status & flags_cmd) == 0U) { 320 if (timeout_elapsed(timeout)) { 321 err = -ETIMEDOUT; 322 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 323 __func__, cmd->cmd_idx, status); 324 goto err_exit; 325 } 326 327 status = mmio_read_32(base + SDMMC_STAR); 328 } 329 330 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 331 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 332 err = -ETIMEDOUT; 333 /* 334 * Those timeouts can occur, and framework will handle 335 * the retries. CMD8 is expected to return this timeout 336 * for eMMC 337 */ 338 if (!((cmd->cmd_idx == MMC_CMD(1)) || 339 (cmd->cmd_idx == MMC_CMD(13)) || 340 ((cmd->cmd_idx == MMC_CMD(8)) && 341 (cmd->resp_type == MMC_RESPONSE_R7)))) { 342 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", 343 __func__, cmd->cmd_idx, status); 344 } 345 } else { 346 err = -EIO; 347 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", 348 __func__, cmd->cmd_idx, status); 349 } 350 351 goto err_exit; 352 } 353 354 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 355 if ((cmd->cmd_idx == MMC_CMD(9)) && 356 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 357 /* Need to invert response to match CSD structure */ 358 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 359 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 360 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 361 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 362 } else { 363 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 364 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 365 SDMMC_CMDR_WAITRESP) { 366 cmd->resp_data[1] = mmio_read_32(base + 367 SDMMC_RESP2R); 368 cmd->resp_data[2] = mmio_read_32(base + 369 SDMMC_RESP3R); 370 cmd->resp_data[3] = mmio_read_32(base + 371 SDMMC_RESP4R); 372 } 373 } 374 } 375 376 if (flags_data == 0U) { 377 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 378 379 return 0; 380 } 381 382 status = mmio_read_32(base + SDMMC_STAR); 383 384 timeout = timeout_init_us(TIMEOUT_US_10_MS); 385 386 while ((status & flags_data) == 0U) { 387 if (timeout_elapsed(timeout)) { 388 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 389 __func__, cmd->cmd_idx, status); 390 err = -ETIMEDOUT; 391 goto err_exit; 392 } 393 394 status = mmio_read_32(base + SDMMC_STAR); 395 }; 396 397 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 398 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 399 SDMMC_STAR_IDMATE)) != 0U) { 400 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, 401 cmd->cmd_idx, status); 402 err = -EIO; 403 } 404 405 err_exit: 406 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 407 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 408 409 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { 410 int ret_stop = stm32_sdmmc2_stop_transfer(); 411 412 if (ret_stop != 0) { 413 return ret_stop; 414 } 415 } 416 417 return err; 418 } 419 420 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 421 { 422 uint8_t retry; 423 int err; 424 425 assert(cmd != NULL); 426 427 for (retry = 0U; retry < 3U; retry++) { 428 err = stm32_sdmmc2_send_cmd_req(cmd); 429 if (err == 0) { 430 return 0; 431 } 432 433 if ((cmd->cmd_idx == MMC_CMD(1)) || 434 (cmd->cmd_idx == MMC_CMD(13))) { 435 return 0; /* Retry managed by framework */ 436 } 437 438 /* Command 8 is expected to fail for eMMC */ 439 if (cmd->cmd_idx != MMC_CMD(8)) { 440 WARN(" CMD%u, Retry: %u, Error: %d\n", 441 cmd->cmd_idx, retry + 1U, err); 442 } 443 444 udelay(10U); 445 } 446 447 return err; 448 } 449 450 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 451 { 452 uintptr_t base = sdmmc2_params.reg_base; 453 uint32_t bus_cfg = 0; 454 uint32_t clock_div, max_freq, freq; 455 uint32_t clk_rate = sdmmc2_params.clk_rate; 456 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 457 458 switch (width) { 459 case MMC_BUS_WIDTH_1: 460 break; 461 case MMC_BUS_WIDTH_4: 462 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 463 break; 464 case MMC_BUS_WIDTH_8: 465 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 466 break; 467 default: 468 panic(); 469 break; 470 } 471 472 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 473 if (max_bus_freq >= 52000000U) { 474 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; 475 } else { 476 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; 477 } 478 } else { 479 if (max_bus_freq >= 50000000U) { 480 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; 481 } else { 482 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; 483 } 484 } 485 486 if (sdmmc2_params.max_freq != 0U) { 487 freq = MIN(sdmmc2_params.max_freq, max_freq); 488 } else { 489 freq = max_freq; 490 } 491 492 clock_div = div_round_up(clk_rate, freq * 2U); 493 494 mmio_write_32(base + SDMMC_CLKCR, 495 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 496 sdmmc2_params.negedge | 497 sdmmc2_params.pin_ckin); 498 499 return 0; 500 } 501 502 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 503 { 504 struct mmc_cmd cmd; 505 int ret; 506 uintptr_t base = sdmmc2_params.reg_base; 507 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 508 uint32_t arg_size; 509 510 assert(size != 0U); 511 512 if (size > MMC_BLOCK_SIZE) { 513 arg_size = MMC_BLOCK_SIZE; 514 } else { 515 arg_size = size; 516 } 517 518 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 519 520 if (sdmmc2_params.use_dma) { 521 inv_dcache_range(buf, size); 522 } 523 524 /* Prepare CMD 16*/ 525 mmio_write_32(base + SDMMC_DTIMER, 0); 526 527 mmio_write_32(base + SDMMC_DLENR, 0); 528 529 mmio_write_32(base + SDMMC_DCTRLR, 0); 530 531 zeromem(&cmd, sizeof(struct mmc_cmd)); 532 533 cmd.cmd_idx = MMC_CMD(16); 534 cmd.cmd_arg = arg_size; 535 cmd.resp_type = MMC_RESPONSE_R1; 536 537 ret = stm32_sdmmc2_send_cmd(&cmd); 538 if (ret != 0) { 539 ERROR("CMD16 failed\n"); 540 return ret; 541 } 542 543 /* Prepare data command */ 544 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 545 546 mmio_write_32(base + SDMMC_DLENR, size); 547 548 if (sdmmc2_params.use_dma) { 549 mmio_write_32(base + SDMMC_IDMACTRLR, 550 SDMMC_IDMACTRLR_IDMAEN); 551 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 552 553 flush_dcache_range(buf, size); 554 } 555 556 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT; 557 558 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 559 SDMMC_DCTRLR_CLEAR_MASK, 560 data_ctrl); 561 562 return 0; 563 } 564 565 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 566 { 567 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 568 SDMMC_STAR_DTIMEOUT; 569 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 570 uint32_t status; 571 uint32_t *buffer; 572 uintptr_t base = sdmmc2_params.reg_base; 573 uintptr_t fifo_reg = base + SDMMC_FIFOR; 574 uint64_t timeout; 575 int ret; 576 577 /* Assert buf is 4 bytes aligned */ 578 assert((buf & GENMASK(1, 0)) == 0U); 579 580 buffer = (uint32_t *)buf; 581 582 if (sdmmc2_params.use_dma) { 583 inv_dcache_range(buf, size); 584 585 return 0; 586 } 587 588 if (size <= MMC_BLOCK_SIZE) { 589 flags |= SDMMC_STAR_DBCKEND; 590 } 591 592 timeout = timeout_init_us(TIMEOUT_US_1_S); 593 594 do { 595 status = mmio_read_32(base + SDMMC_STAR); 596 597 if ((status & error_flags) != 0U) { 598 ERROR("%s: Read error (status = %x)\n", __func__, 599 status); 600 mmio_write_32(base + SDMMC_DCTRLR, 601 SDMMC_DCTRLR_FIFORST); 602 603 mmio_write_32(base + SDMMC_ICR, 604 SDMMC_STATIC_FLAGS); 605 606 ret = stm32_sdmmc2_stop_transfer(); 607 if (ret != 0) { 608 return ret; 609 } 610 611 return -EIO; 612 } 613 614 if (timeout_elapsed(timeout)) { 615 ERROR("%s: timeout 1s (status = %x)\n", 616 __func__, status); 617 mmio_write_32(base + SDMMC_ICR, 618 SDMMC_STATIC_FLAGS); 619 620 ret = stm32_sdmmc2_stop_transfer(); 621 if (ret != 0) { 622 return ret; 623 } 624 625 return -ETIMEDOUT; 626 } 627 628 if (size < (8U * sizeof(uint32_t))) { 629 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 630 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 631 *buffer = mmio_read_32(fifo_reg); 632 buffer++; 633 } 634 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 635 uint32_t count; 636 637 /* Read data from SDMMC Rx FIFO */ 638 for (count = 0; count < 8U; count++) { 639 *buffer = mmio_read_32(fifo_reg); 640 buffer++; 641 } 642 } 643 } while ((status & flags) == 0U); 644 645 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 646 647 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 648 WARN("%s: DPSMACT=1, send stop\n", __func__); 649 return stm32_sdmmc2_stop_transfer(); 650 } 651 652 return 0; 653 } 654 655 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 656 { 657 return 0; 658 } 659 660 static int stm32_sdmmc2_dt_get_config(void) 661 { 662 int sdmmc_node; 663 void *fdt = NULL; 664 const fdt32_t *cuint; 665 struct dt_node_info dt_info; 666 667 if (fdt_get_address(&fdt) == 0) { 668 return -FDT_ERR_NOTFOUND; 669 } 670 671 if (fdt == NULL) { 672 return -FDT_ERR_NOTFOUND; 673 } 674 675 sdmmc_node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT, 676 sdmmc2_params.reg_base); 677 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 678 return -FDT_ERR_NOTFOUND; 679 } 680 681 dt_fill_device_info(&dt_info, sdmmc_node); 682 if (dt_info.status == DT_DISABLED) { 683 return -FDT_ERR_NOTFOUND; 684 } 685 686 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 687 return -FDT_ERR_BADVALUE; 688 } 689 690 sdmmc2_params.clock_id = dt_info.clock; 691 sdmmc2_params.reset_id = dt_info.reset; 692 693 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 694 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 695 } 696 697 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 698 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 699 } 700 701 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 702 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 703 } 704 705 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 706 if (cuint != NULL) { 707 switch (fdt32_to_cpu(*cuint)) { 708 case 4: 709 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 710 break; 711 712 case 8: 713 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 714 break; 715 716 default: 717 break; 718 } 719 } 720 721 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); 722 if (cuint != NULL) { 723 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); 724 } 725 726 sdmmc2_params.vmmc_regu = regulator_get_by_supply_name(fdt, sdmmc_node, "vmmc"); 727 728 return 0; 729 } 730 731 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 732 { 733 return sdmmc2_params.device_info->device_size; 734 } 735 736 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 737 { 738 int rc; 739 740 assert((params != NULL) && 741 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 742 ((params->bus_width == MMC_BUS_WIDTH_1) || 743 (params->bus_width == MMC_BUS_WIDTH_4) || 744 (params->bus_width == MMC_BUS_WIDTH_8))); 745 746 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 747 748 sdmmc2_params.vmmc_regu = NULL; 749 750 if (stm32_sdmmc2_dt_get_config() != 0) { 751 ERROR("%s: DT error\n", __func__); 752 return -ENOMEM; 753 } 754 755 clk_enable(sdmmc2_params.clock_id); 756 757 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 758 if (rc != 0) { 759 panic(); 760 } 761 udelay(2); 762 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 763 if (rc != 0) { 764 panic(); 765 } 766 mdelay(1); 767 768 sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); 769 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 770 771 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 772 sdmmc2_params.bus_width, sdmmc2_params.flags, 773 sdmmc2_params.device_info); 774 } 775