1/* 2 * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache 15 * --------------------------------------------- 16 */ 17func cortex_a73_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a73_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable intra-cluster coherency 27 * --------------------------------------------- 28 */ 29func cortex_a73_disable_smp 30 mrs x0, CORTEX_A73_CPUECTLR_EL1 31 bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 32 msr CORTEX_A73_CPUECTLR_EL1, x0 33 isb 34 dsb sy 35 ret 36endfunc cortex_a73_disable_smp 37 38 /* --------------------------------------------------- 39 * Errata Workaround for Cortex A73 Errata #852427. 40 * This applies only to revision r0p0 of Cortex A73. 41 * Inputs: 42 * x0: variant[4:7] and revision[0:3] of current cpu. 43 * Shall clobber: x0-x17 44 * --------------------------------------------------- 45 */ 46func errata_a73_852427_wa 47 /* 48 * Compare x0 against revision r0p0 49 */ 50 mov x17, x30 51 bl check_errata_852427 52 cbz x0, 1f 53 mrs x1, CORTEX_A73_DIAGNOSTIC_REGISTER 54 orr x1, x1, #(1 << 12) 55 msr CORTEX_A73_DIAGNOSTIC_REGISTER, x1 56 isb 571: 58 ret x17 59endfunc errata_a73_852427_wa 60 61func check_errata_852427 62 mov x1, #0x00 63 b cpu_rev_var_ls 64endfunc check_errata_852427 65 66 /* --------------------------------------------------- 67 * Errata Workaround for Cortex A73 Errata #855423. 68 * This applies only to revision <= r0p1 of Cortex A73. 69 * Inputs: 70 * x0: variant[4:7] and revision[0:3] of current cpu. 71 * Shall clobber: x0-x17 72 * --------------------------------------------------- 73 */ 74func errata_a73_855423_wa 75 /* 76 * Compare x0 against revision r0p1 77 */ 78 mov x17, x30 79 bl check_errata_855423 80 cbz x0, 1f 81 mrs x1, CORTEX_A73_IMP_DEF_REG2 82 orr x1, x1, #(1 << 7) 83 msr CORTEX_A73_IMP_DEF_REG2, x1 84 isb 851: 86 ret x17 87endfunc errata_a73_855423_wa 88 89func check_errata_855423 90 mov x1, #0x01 91 b cpu_rev_var_ls 92endfunc check_errata_855423 93 94 /* ------------------------------------------------- 95 * The CPU Ops reset function for Cortex-A73. 96 * ------------------------------------------------- 97 */ 98 99func cortex_a73_reset_func 100 mov x19, x30 101 bl cpu_get_rev_var 102 mov x18, x0 103 104#if ERRATA_A73_852427 105 mov x0, x18 106 bl errata_a73_852427_wa 107#endif 108 109#if ERRATA_A73_855423 110 mov x0, x18 111 bl errata_a73_855423_wa 112#endif 113 114#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) 115 cpu_check_csv2 x0, 1f 116 adr x0, wa_cve_2017_5715_bpiall_vbar 117 msr vbar_el3, x0 118 isb 119 /* Skip installing vector table again for CVE_2022_23960 */ 120 b 2f 1211: 122#if WORKAROUND_CVE_2022_23960 123 adr x0, wa_cve_2017_5715_bpiall_vbar 124 msr vbar_el3, x0 125 isb 126#endif 1272: 128#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */ 129 130#if WORKAROUND_CVE_2018_3639 131 mrs x0, CORTEX_A73_IMP_DEF_REG1 132 orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 133 msr CORTEX_A73_IMP_DEF_REG1, x0 134 isb 135#endif 136 137 /* --------------------------------------------- 138 * Enable the SMP bit. 139 * Clobbers : x0 140 * --------------------------------------------- 141 */ 142 mrs x0, CORTEX_A73_CPUECTLR_EL1 143 orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 144 msr CORTEX_A73_CPUECTLR_EL1, x0 145 isb 146 ret x19 147endfunc cortex_a73_reset_func 148 149func cortex_a73_core_pwr_dwn 150 mov x18, x30 151 152 /* --------------------------------------------- 153 * Turn off caches. 154 * --------------------------------------------- 155 */ 156 bl cortex_a73_disable_dcache 157 158 /* --------------------------------------------- 159 * Flush L1 caches. 160 * --------------------------------------------- 161 */ 162 mov x0, #DCCISW 163 bl dcsw_op_level1 164 165 /* --------------------------------------------- 166 * Come out of intra cluster coherency 167 * --------------------------------------------- 168 */ 169 mov x30, x18 170 b cortex_a73_disable_smp 171endfunc cortex_a73_core_pwr_dwn 172 173func cortex_a73_cluster_pwr_dwn 174 mov x18, x30 175 176 /* --------------------------------------------- 177 * Turn off caches. 178 * --------------------------------------------- 179 */ 180 bl cortex_a73_disable_dcache 181 182 /* --------------------------------------------- 183 * Flush L1 caches. 184 * --------------------------------------------- 185 */ 186 mov x0, #DCCISW 187 bl dcsw_op_level1 188 189 /* --------------------------------------------- 190 * Disable the optional ACP. 191 * --------------------------------------------- 192 */ 193 bl plat_disable_acp 194 195 /* --------------------------------------------- 196 * Flush L2 caches. 197 * --------------------------------------------- 198 */ 199 mov x0, #DCCISW 200 bl dcsw_op_level2 201 202 /* --------------------------------------------- 203 * Come out of intra cluster coherency 204 * --------------------------------------------- 205 */ 206 mov x30, x18 207 b cortex_a73_disable_smp 208endfunc cortex_a73_cluster_pwr_dwn 209 210func check_errata_cve_2017_5715 211 cpu_check_csv2 x0, 1f 212#if WORKAROUND_CVE_2017_5715 213 mov x0, #ERRATA_APPLIES 214#else 215 mov x0, #ERRATA_MISSING 216#endif 217 ret 2181: 219 mov x0, #ERRATA_NOT_APPLIES 220 ret 221endfunc check_errata_cve_2017_5715 222 223func check_errata_cve_2018_3639 224#if WORKAROUND_CVE_2018_3639 225 mov x0, #ERRATA_APPLIES 226#else 227 mov x0, #ERRATA_MISSING 228#endif 229 ret 230endfunc check_errata_cve_2018_3639 231 232func check_errata_cve_2022_23960 233#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 234 cpu_check_csv2 x0, 1f 235 mov x0, #ERRATA_APPLIES 236 ret 237 1: 238# if WORKAROUND_CVE_2022_23960 239 mov x0, #ERRATA_APPLIES 240# else 241 mov x0, #ERRATA_MISSING 242# endif /* WORKAROUND_CVE_2022_23960 */ 243 ret 244#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 245 mov x0, #ERRATA_MISSING 246 ret 247endfunc check_errata_cve_2022_23960 248 249func check_smccc_arch_workaround_3 250 mov x0, #ERRATA_APPLIES 251 ret 252endfunc check_smccc_arch_workaround_3 253 254#if REPORT_ERRATA 255/* 256 * Errata printing function for Cortex A75. Must follow AAPCS. 257 */ 258func cortex_a73_errata_report 259 stp x8, x30, [sp, #-16]! 260 261 bl cpu_get_rev_var 262 mov x8, x0 263 264 /* 265 * Report all errata. The revision-variant information is passed to 266 * checking functions of each errata. 267 */ 268 report_errata ERRATA_A73_852427, cortex_a73, 852427 269 report_errata ERRATA_A73_855423, cortex_a73, 855423 270 report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715 271 report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639 272 report_errata WORKAROUND_CVE_2022_23960, cortex_a73, cve_2022_23960 273 274 ldp x8, x30, [sp], #16 275 ret 276endfunc cortex_a73_errata_report 277#endif 278 279 /* --------------------------------------------- 280 * This function provides cortex_a73 specific 281 * register information for crash reporting. 282 * It needs to return with x6 pointing to 283 * a list of register names in ascii and 284 * x8 - x15 having values of registers to be 285 * reported. 286 * --------------------------------------------- 287 */ 288.section .rodata.cortex_a73_regs, "aS" 289cortex_a73_regs: /* The ascii list of register names to be reported */ 290 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 291 292func cortex_a73_cpu_reg_dump 293 adr x6, cortex_a73_regs 294 mrs x8, CORTEX_A73_CPUECTLR_EL1 295 mrs x9, CORTEX_A73_L2MERRSR_EL1 296 ret 297endfunc cortex_a73_cpu_reg_dump 298 299declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ 300 cortex_a73_reset_func, \ 301 check_errata_cve_2017_5715, \ 302 CPU_NO_EXTRA2_FUNC, \ 303 check_smccc_arch_workaround_3, \ 304 cortex_a73_core_pwr_dwn, \ 305 cortex_a73_cluster_pwr_dwn 306