1 /* 2 * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/clk.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/stm32_gpio.h> 18 #include <drivers/st/stm32_sdmmc2.h> 19 #include <drivers/st/stm32mp_reset.h> 20 #include <lib/mmio.h> 21 #include <lib/utils.h> 22 #include <libfdt.h> 23 #include <plat/common/platform.h> 24 25 #include <platform_def.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_PWRCTRL_PWR_CYCLE BIT(1) 54 #define SDMMC_POWER_DIRPOL BIT(4) 55 56 /* SDMMC clock control register */ 57 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 58 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 59 #define SDMMC_CLKCR_NEGEDGE BIT(16) 60 #define SDMMC_CLKCR_HWFC_EN BIT(17) 61 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 62 63 /* SDMMC command register */ 64 #define SDMMC_CMDR_CMDTRANS BIT(6) 65 #define SDMMC_CMDR_CMDSTOP BIT(7) 66 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 67 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 68 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 69 #define SDMMC_CMDR_CPSMEN BIT(12) 70 71 /* SDMMC data control register */ 72 #define SDMMC_DCTRLR_DTEN BIT(0) 73 #define SDMMC_DCTRLR_DTDIR BIT(1) 74 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 75 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4 77 #define SDMMC_DCTRLR_FIFORST BIT(13) 78 79 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 80 SDMMC_DCTRLR_DTDIR | \ 81 SDMMC_DCTRLR_DTMODE | \ 82 SDMMC_DCTRLR_DBLOCKSIZE) 83 84 /* SDMMC status register */ 85 #define SDMMC_STAR_CCRCFAIL BIT(0) 86 #define SDMMC_STAR_DCRCFAIL BIT(1) 87 #define SDMMC_STAR_CTIMEOUT BIT(2) 88 #define SDMMC_STAR_DTIMEOUT BIT(3) 89 #define SDMMC_STAR_TXUNDERR BIT(4) 90 #define SDMMC_STAR_RXOVERR BIT(5) 91 #define SDMMC_STAR_CMDREND BIT(6) 92 #define SDMMC_STAR_CMDSENT BIT(7) 93 #define SDMMC_STAR_DATAEND BIT(8) 94 #define SDMMC_STAR_DBCKEND BIT(10) 95 #define SDMMC_STAR_DPSMACT BIT(12) 96 #define SDMMC_STAR_RXFIFOHF BIT(15) 97 #define SDMMC_STAR_RXFIFOE BIT(19) 98 #define SDMMC_STAR_IDMATE BIT(27) 99 #define SDMMC_STAR_IDMABTC BIT(28) 100 101 /* SDMMC DMA control register */ 102 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 103 104 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 105 SDMMC_STAR_DCRCFAIL | \ 106 SDMMC_STAR_CTIMEOUT | \ 107 SDMMC_STAR_DTIMEOUT | \ 108 SDMMC_STAR_TXUNDERR | \ 109 SDMMC_STAR_RXOVERR | \ 110 SDMMC_STAR_CMDREND | \ 111 SDMMC_STAR_CMDSENT | \ 112 SDMMC_STAR_DATAEND | \ 113 SDMMC_STAR_DBCKEND | \ 114 SDMMC_STAR_IDMATE | \ 115 SDMMC_STAR_IDMABTC) 116 117 #define TIMEOUT_US_1_MS 1000U 118 #define TIMEOUT_US_10_MS 10000U 119 #define TIMEOUT_US_1_S 1000000U 120 121 /* Power cycle delays in ms */ 122 #define VCC_POWER_OFF_DELAY 2 123 #define VCC_POWER_ON_DELAY 2 124 #define POWER_CYCLE_DELAY 2 125 #define POWER_OFF_DELAY 2 126 #define POWER_ON_DELAY 1 127 128 #ifndef DT_SDMMC2_COMPAT 129 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 130 #endif 131 132 static void stm32_sdmmc2_init(void); 133 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 134 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 135 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 136 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 137 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 138 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 139 140 static const struct mmc_ops stm32_sdmmc2_ops = { 141 .init = stm32_sdmmc2_init, 142 .send_cmd = stm32_sdmmc2_send_cmd, 143 .set_ios = stm32_sdmmc2_set_ios, 144 .prepare = stm32_sdmmc2_prepare, 145 .read = stm32_sdmmc2_read, 146 .write = stm32_sdmmc2_write, 147 }; 148 149 static struct stm32_sdmmc2_params sdmmc2_params; 150 151 #pragma weak plat_sdmmc2_use_dma 152 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 153 { 154 return false; 155 } 156 157 static void stm32_sdmmc2_init(void) 158 { 159 uint32_t clock_div; 160 uint32_t freq = STM32MP_MMC_INIT_FREQ; 161 uintptr_t base = sdmmc2_params.reg_base; 162 int ret; 163 164 if (sdmmc2_params.max_freq != 0U) { 165 freq = MIN(sdmmc2_params.max_freq, freq); 166 } 167 168 if (sdmmc2_params.vmmc_regu != NULL) { 169 ret = regulator_disable(sdmmc2_params.vmmc_regu); 170 if (ret < 0) { 171 panic(); 172 } 173 } 174 175 mdelay(VCC_POWER_OFF_DELAY); 176 177 mmio_write_32(base + SDMMC_POWER, 178 SDMMC_POWER_PWRCTRL_PWR_CYCLE | sdmmc2_params.dirpol); 179 mdelay(POWER_CYCLE_DELAY); 180 181 if (sdmmc2_params.vmmc_regu != NULL) { 182 ret = regulator_enable(sdmmc2_params.vmmc_regu); 183 if (ret < 0) { 184 panic(); 185 } 186 } 187 188 mdelay(VCC_POWER_ON_DELAY); 189 190 mmio_write_32(base + SDMMC_POWER, sdmmc2_params.dirpol); 191 mdelay(POWER_OFF_DELAY); 192 193 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); 194 195 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 196 sdmmc2_params.negedge | 197 sdmmc2_params.pin_ckin); 198 199 mmio_write_32(base + SDMMC_POWER, 200 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 201 202 mdelay(POWER_ON_DELAY); 203 } 204 205 static int stm32_sdmmc2_stop_transfer(void) 206 { 207 struct mmc_cmd cmd_stop; 208 209 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 210 211 cmd_stop.cmd_idx = MMC_CMD(12); 212 cmd_stop.resp_type = MMC_RESPONSE_R1B; 213 214 return stm32_sdmmc2_send_cmd(&cmd_stop); 215 } 216 217 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 218 { 219 uint64_t timeout; 220 uint32_t flags_cmd, status; 221 uint32_t flags_data = 0; 222 int err = 0; 223 uintptr_t base = sdmmc2_params.reg_base; 224 unsigned int cmd_reg, arg_reg; 225 226 if (cmd == NULL) { 227 return -EINVAL; 228 } 229 230 flags_cmd = SDMMC_STAR_CTIMEOUT; 231 arg_reg = cmd->cmd_arg; 232 233 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 234 mmio_write_32(base + SDMMC_CMDR, 0); 235 } 236 237 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 238 239 if (cmd->resp_type == 0U) { 240 flags_cmd |= SDMMC_STAR_CMDSENT; 241 } 242 243 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 244 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 245 flags_cmd |= SDMMC_STAR_CMDREND; 246 cmd_reg |= SDMMC_CMDR_WAITRESP; 247 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 248 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 249 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 250 } else { 251 flags_cmd |= SDMMC_STAR_CMDREND; 252 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 253 } 254 } 255 256 switch (cmd->cmd_idx) { 257 case MMC_CMD(1): 258 arg_reg |= OCR_POWERUP; 259 break; 260 case MMC_CMD(8): 261 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 262 cmd_reg |= SDMMC_CMDR_CMDTRANS; 263 } 264 break; 265 case MMC_CMD(12): 266 cmd_reg |= SDMMC_CMDR_CMDSTOP; 267 break; 268 case MMC_CMD(17): 269 case MMC_CMD(18): 270 cmd_reg |= SDMMC_CMDR_CMDTRANS; 271 if (sdmmc2_params.use_dma) { 272 flags_data |= SDMMC_STAR_DCRCFAIL | 273 SDMMC_STAR_DTIMEOUT | 274 SDMMC_STAR_DATAEND | 275 SDMMC_STAR_RXOVERR | 276 SDMMC_STAR_IDMATE; 277 } 278 break; 279 case MMC_ACMD(41): 280 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 281 break; 282 case MMC_ACMD(51): 283 cmd_reg |= SDMMC_CMDR_CMDTRANS; 284 if (sdmmc2_params.use_dma) { 285 flags_data |= SDMMC_STAR_DCRCFAIL | 286 SDMMC_STAR_DTIMEOUT | 287 SDMMC_STAR_DATAEND | 288 SDMMC_STAR_RXOVERR | 289 SDMMC_STAR_IDMATE | 290 SDMMC_STAR_DBCKEND; 291 } 292 break; 293 default: 294 break; 295 } 296 297 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 298 299 /* 300 * Clear the SDMMC_DCTRLR if the command does not await data. 301 * Skip CMD55 as the next command could be data related, and 302 * the register could have been set in prepare function. 303 */ 304 if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) && 305 (cmd->cmd_idx != MMC_CMD(55))) { 306 mmio_write_32(base + SDMMC_DCTRLR, 0U); 307 } 308 309 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 310 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 311 } 312 313 mmio_write_32(base + SDMMC_ARGR, arg_reg); 314 315 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 316 317 status = mmio_read_32(base + SDMMC_STAR); 318 319 timeout = timeout_init_us(TIMEOUT_US_10_MS); 320 321 while ((status & flags_cmd) == 0U) { 322 if (timeout_elapsed(timeout)) { 323 err = -ETIMEDOUT; 324 ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n", 325 __func__, cmd->cmd_idx, status); 326 goto err_exit; 327 } 328 329 status = mmio_read_32(base + SDMMC_STAR); 330 } 331 332 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 333 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 334 err = -ETIMEDOUT; 335 /* 336 * Those timeouts can occur, and framework will handle 337 * the retries. CMD8 is expected to return this timeout 338 * for eMMC 339 */ 340 if (!((cmd->cmd_idx == MMC_CMD(1)) || 341 (cmd->cmd_idx == MMC_CMD(13)) || 342 ((cmd->cmd_idx == MMC_CMD(8)) && 343 (cmd->resp_type == MMC_RESPONSE_R7)))) { 344 ERROR("%s: CTIMEOUT (cmd = %u,status = %x)\n", 345 __func__, cmd->cmd_idx, status); 346 } 347 } else { 348 err = -EIO; 349 ERROR("%s: CRCFAIL (cmd = %u,status = %x)\n", 350 __func__, cmd->cmd_idx, status); 351 } 352 353 goto err_exit; 354 } 355 356 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 357 if ((cmd->cmd_idx == MMC_CMD(9)) && 358 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 359 /* Need to invert response to match CSD structure */ 360 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 361 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 362 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 363 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 364 } else { 365 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 366 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 367 SDMMC_CMDR_WAITRESP) { 368 cmd->resp_data[1] = mmio_read_32(base + 369 SDMMC_RESP2R); 370 cmd->resp_data[2] = mmio_read_32(base + 371 SDMMC_RESP3R); 372 cmd->resp_data[3] = mmio_read_32(base + 373 SDMMC_RESP4R); 374 } 375 } 376 } 377 378 if (flags_data == 0U) { 379 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 380 381 return 0; 382 } 383 384 status = mmio_read_32(base + SDMMC_STAR); 385 386 timeout = timeout_init_us(TIMEOUT_US_10_MS); 387 388 while ((status & flags_data) == 0U) { 389 if (timeout_elapsed(timeout)) { 390 ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n", 391 __func__, cmd->cmd_idx, status); 392 err = -ETIMEDOUT; 393 goto err_exit; 394 } 395 396 status = mmio_read_32(base + SDMMC_STAR); 397 }; 398 399 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 400 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 401 SDMMC_STAR_IDMATE)) != 0U) { 402 ERROR("%s: Error flag (cmd = %u,status = %x)\n", __func__, 403 cmd->cmd_idx, status); 404 err = -EIO; 405 } 406 407 err_exit: 408 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 409 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 410 411 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { 412 int ret_stop = stm32_sdmmc2_stop_transfer(); 413 414 if (ret_stop != 0) { 415 return ret_stop; 416 } 417 } 418 419 return err; 420 } 421 422 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 423 { 424 uint8_t retry; 425 int err; 426 427 assert(cmd != NULL); 428 429 for (retry = 0U; retry < 3U; retry++) { 430 err = stm32_sdmmc2_send_cmd_req(cmd); 431 if (err == 0) { 432 return 0; 433 } 434 435 if ((cmd->cmd_idx == MMC_CMD(1)) || 436 (cmd->cmd_idx == MMC_CMD(13))) { 437 return 0; /* Retry managed by framework */ 438 } 439 440 /* Command 8 is expected to fail for eMMC */ 441 if (cmd->cmd_idx != MMC_CMD(8)) { 442 WARN(" CMD%u, Retry: %u, Error: %d\n", 443 cmd->cmd_idx, retry + 1U, err); 444 } 445 446 udelay(10U); 447 } 448 449 return err; 450 } 451 452 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 453 { 454 uintptr_t base = sdmmc2_params.reg_base; 455 uint32_t bus_cfg = 0; 456 uint32_t clock_div, max_freq, freq; 457 uint32_t clk_rate = sdmmc2_params.clk_rate; 458 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 459 460 switch (width) { 461 case MMC_BUS_WIDTH_1: 462 break; 463 case MMC_BUS_WIDTH_4: 464 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 465 break; 466 case MMC_BUS_WIDTH_8: 467 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 468 break; 469 default: 470 panic(); 471 break; 472 } 473 474 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 475 if (max_bus_freq >= 52000000U) { 476 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; 477 } else { 478 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; 479 } 480 } else { 481 if (max_bus_freq >= 50000000U) { 482 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; 483 } else { 484 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; 485 } 486 } 487 488 if (sdmmc2_params.max_freq != 0U) { 489 freq = MIN(sdmmc2_params.max_freq, max_freq); 490 } else { 491 freq = max_freq; 492 } 493 494 clock_div = div_round_up(clk_rate, freq * 2U); 495 496 mmio_write_32(base + SDMMC_CLKCR, 497 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 498 sdmmc2_params.negedge | 499 sdmmc2_params.pin_ckin); 500 501 return 0; 502 } 503 504 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 505 { 506 struct mmc_cmd cmd; 507 int ret; 508 uintptr_t base = sdmmc2_params.reg_base; 509 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 510 uint32_t arg_size; 511 512 assert(size != 0U); 513 514 if (size > MMC_BLOCK_SIZE) { 515 arg_size = MMC_BLOCK_SIZE; 516 } else { 517 arg_size = size; 518 } 519 520 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 521 522 if (sdmmc2_params.use_dma) { 523 inv_dcache_range(buf, size); 524 } 525 526 /* Prepare CMD 16*/ 527 mmio_write_32(base + SDMMC_DTIMER, 0); 528 529 mmio_write_32(base + SDMMC_DLENR, 0); 530 531 mmio_write_32(base + SDMMC_DCTRLR, 0); 532 533 zeromem(&cmd, sizeof(struct mmc_cmd)); 534 535 cmd.cmd_idx = MMC_CMD(16); 536 cmd.cmd_arg = arg_size; 537 cmd.resp_type = MMC_RESPONSE_R1; 538 539 ret = stm32_sdmmc2_send_cmd(&cmd); 540 if (ret != 0) { 541 ERROR("CMD16 failed\n"); 542 return ret; 543 } 544 545 /* Prepare data command */ 546 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 547 548 mmio_write_32(base + SDMMC_DLENR, size); 549 550 if (sdmmc2_params.use_dma) { 551 mmio_write_32(base + SDMMC_IDMACTRLR, 552 SDMMC_IDMACTRLR_IDMAEN); 553 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 554 555 flush_dcache_range(buf, size); 556 } 557 558 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT; 559 560 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 561 SDMMC_DCTRLR_CLEAR_MASK, 562 data_ctrl); 563 564 return 0; 565 } 566 567 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 568 { 569 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 570 SDMMC_STAR_DTIMEOUT; 571 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 572 uint32_t status; 573 uint32_t *buffer; 574 uintptr_t base = sdmmc2_params.reg_base; 575 uintptr_t fifo_reg = base + SDMMC_FIFOR; 576 uint64_t timeout; 577 int ret; 578 579 /* Assert buf is 4 bytes aligned */ 580 assert((buf & GENMASK(1, 0)) == 0U); 581 582 buffer = (uint32_t *)buf; 583 584 if (sdmmc2_params.use_dma) { 585 inv_dcache_range(buf, size); 586 587 return 0; 588 } 589 590 if (size <= MMC_BLOCK_SIZE) { 591 flags |= SDMMC_STAR_DBCKEND; 592 } 593 594 timeout = timeout_init_us(TIMEOUT_US_1_S); 595 596 do { 597 status = mmio_read_32(base + SDMMC_STAR); 598 599 if ((status & error_flags) != 0U) { 600 ERROR("%s: Read error (status = %x)\n", __func__, 601 status); 602 mmio_write_32(base + SDMMC_DCTRLR, 603 SDMMC_DCTRLR_FIFORST); 604 605 mmio_write_32(base + SDMMC_ICR, 606 SDMMC_STATIC_FLAGS); 607 608 ret = stm32_sdmmc2_stop_transfer(); 609 if (ret != 0) { 610 return ret; 611 } 612 613 return -EIO; 614 } 615 616 if (timeout_elapsed(timeout)) { 617 ERROR("%s: timeout 1s (status = %x)\n", 618 __func__, status); 619 mmio_write_32(base + SDMMC_ICR, 620 SDMMC_STATIC_FLAGS); 621 622 ret = stm32_sdmmc2_stop_transfer(); 623 if (ret != 0) { 624 return ret; 625 } 626 627 return -ETIMEDOUT; 628 } 629 630 if (size < (8U * sizeof(uint32_t))) { 631 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 632 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 633 *buffer = mmio_read_32(fifo_reg); 634 buffer++; 635 } 636 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 637 uint32_t count; 638 639 /* Read data from SDMMC Rx FIFO */ 640 for (count = 0; count < 8U; count++) { 641 *buffer = mmio_read_32(fifo_reg); 642 buffer++; 643 } 644 } 645 } while ((status & flags) == 0U); 646 647 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 648 649 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 650 WARN("%s: DPSMACT=1, send stop\n", __func__); 651 return stm32_sdmmc2_stop_transfer(); 652 } 653 654 return 0; 655 } 656 657 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 658 { 659 return 0; 660 } 661 662 static int stm32_sdmmc2_dt_get_config(void) 663 { 664 int sdmmc_node; 665 void *fdt = NULL; 666 const fdt32_t *cuint; 667 struct dt_node_info dt_info; 668 669 if (fdt_get_address(&fdt) == 0) { 670 return -FDT_ERR_NOTFOUND; 671 } 672 673 if (fdt == NULL) { 674 return -FDT_ERR_NOTFOUND; 675 } 676 677 sdmmc_node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT, 678 sdmmc2_params.reg_base); 679 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 680 return -FDT_ERR_NOTFOUND; 681 } 682 683 dt_fill_device_info(&dt_info, sdmmc_node); 684 if (dt_info.status == DT_DISABLED) { 685 return -FDT_ERR_NOTFOUND; 686 } 687 688 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 689 return -FDT_ERR_BADVALUE; 690 } 691 692 sdmmc2_params.clock_id = dt_info.clock; 693 sdmmc2_params.reset_id = dt_info.reset; 694 695 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 696 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 697 } 698 699 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 700 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 701 } 702 703 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 704 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 705 } 706 707 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 708 if (cuint != NULL) { 709 switch (fdt32_to_cpu(*cuint)) { 710 case 4: 711 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 712 break; 713 714 case 8: 715 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 716 break; 717 718 default: 719 break; 720 } 721 } 722 723 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); 724 if (cuint != NULL) { 725 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); 726 } 727 728 sdmmc2_params.vmmc_regu = regulator_get_by_supply_name(fdt, sdmmc_node, "vmmc"); 729 730 return 0; 731 } 732 733 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 734 { 735 return sdmmc2_params.device_info->device_size; 736 } 737 738 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 739 { 740 int rc; 741 742 assert((params != NULL) && 743 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 744 ((params->bus_width == MMC_BUS_WIDTH_1) || 745 (params->bus_width == MMC_BUS_WIDTH_4) || 746 (params->bus_width == MMC_BUS_WIDTH_8))); 747 748 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 749 750 sdmmc2_params.vmmc_regu = NULL; 751 752 if (stm32_sdmmc2_dt_get_config() != 0) { 753 ERROR("%s: DT error\n", __func__); 754 return -ENOMEM; 755 } 756 757 clk_enable(sdmmc2_params.clock_id); 758 759 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 760 if (rc != 0) { 761 panic(); 762 } 763 udelay(2); 764 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 765 if (rc != 0) { 766 panic(); 767 } 768 mdelay(1); 769 770 sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); 771 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 772 773 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 774 sdmmc2_params.bus_width, sdmmc2_params.flags, 775 sdmmc2_params.device_info); 776 } 777