xref: /rk3399_ARM-atf/plat/intel/soc/common/include/socfpga_fcs.h (revision f2de48cb143c20ccd7a9c141df3d34cae74049de)
1 /*
2  * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SOCFPGA_FCS_H
8 #define SOCFPGA_FCS_H
9 
10 /* FCS Definitions */
11 
12 #define FCS_RANDOM_WORD_SIZE		8U
13 #define FCS_PROV_DATA_WORD_SIZE		44U
14 
15 #define FCS_RANDOM_BYTE_SIZE		(FCS_RANDOM_WORD_SIZE * 4U)
16 #define FCS_PROV_DATA_BYTE_SIZE		(FCS_PROV_DATA_WORD_SIZE * 4U)
17 
18 #define FCS_CRYPTION_DATA_0		0x10100
19 
20 /* FCS Payload Structure */
21 
22 typedef struct fcs_crypt_payload_t {
23 	uint32_t first_word;
24 	uint32_t src_addr;
25 	uint32_t src_size;
26 	uint32_t dst_addr;
27 	uint32_t dst_size;
28 } fcs_crypt_payload;
29 
30 /* Functions Definitions */
31 
32 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size,
33 				uint32_t *mbox_error);
34 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
35 				uint32_t *send_id);
36 uint32_t intel_fcs_get_provision_data(uint32_t *send_id);
37 uint32_t intel_fcs_cryption(uint32_t mode, uint32_t src_addr,
38 			uint32_t src_size, uint32_t dst_addr,
39 			uint32_t dst_size, uint32_t *send_id);
40 
41 #endif /* SOCFPGA_FCS_H */
42