1 /* 2 * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <common/debug.h> 10 #include <drivers/nand.h> 11 #include <drivers/raw_nand.h> 12 #include <drivers/spi_nand.h> 13 #include <drivers/spi_nor.h> 14 #include <lib/utils.h> 15 #include <plat/common/platform.h> 16 17 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 18 static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc) 19 { 20 uint32_t nand_param; 21 22 /* Check if NAND parameters are stored in OTP */ 23 if (stm32_get_otp_value(NAND_OTP, &nand_param) != 0) { 24 ERROR("BSEC: NAND_OTP Error\n"); 25 return -EACCES; 26 } 27 28 if (nand_param == 0U) { 29 return 0; 30 } 31 32 if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) { 33 goto ecc; 34 } 35 36 /* NAND parameter shall be read from OTP */ 37 if ((nand_param & NAND_WIDTH_MASK) != 0U) { 38 nand_dev->buswidth = NAND_BUS_WIDTH_16; 39 } else { 40 nand_dev->buswidth = NAND_BUS_WIDTH_8; 41 } 42 43 switch ((nand_param & NAND_PAGE_SIZE_MASK) >> NAND_PAGE_SIZE_SHIFT) { 44 case NAND_PAGE_SIZE_2K: 45 nand_dev->page_size = 0x800U; 46 break; 47 48 case NAND_PAGE_SIZE_4K: 49 nand_dev->page_size = 0x1000U; 50 break; 51 52 case NAND_PAGE_SIZE_8K: 53 nand_dev->page_size = 0x2000U; 54 break; 55 56 default: 57 ERROR("Cannot read NAND page size\n"); 58 return -EINVAL; 59 } 60 61 switch ((nand_param & NAND_BLOCK_SIZE_MASK) >> NAND_BLOCK_SIZE_SHIFT) { 62 case NAND_BLOCK_SIZE_64_PAGES: 63 nand_dev->block_size = 64U * nand_dev->page_size; 64 break; 65 66 case NAND_BLOCK_SIZE_128_PAGES: 67 nand_dev->block_size = 128U * nand_dev->page_size; 68 break; 69 70 case NAND_BLOCK_SIZE_256_PAGES: 71 nand_dev->block_size = 256U * nand_dev->page_size; 72 break; 73 74 default: 75 ERROR("Cannot read NAND block size\n"); 76 return -EINVAL; 77 } 78 79 nand_dev->size = ((nand_param & NAND_BLOCK_NB_MASK) >> 80 NAND_BLOCK_NB_SHIFT) * 81 NAND_BLOCK_NB_UNIT * nand_dev->block_size; 82 83 ecc: 84 if (is_slc) { 85 switch ((nand_param & NAND_ECC_BIT_NB_MASK) >> 86 NAND_ECC_BIT_NB_SHIFT) { 87 case NAND_ECC_BIT_NB_1_BITS: 88 nand_dev->ecc.max_bit_corr = 1U; 89 break; 90 91 case NAND_ECC_BIT_NB_4_BITS: 92 nand_dev->ecc.max_bit_corr = 4U; 93 break; 94 95 case NAND_ECC_BIT_NB_8_BITS: 96 nand_dev->ecc.max_bit_corr = 8U; 97 break; 98 99 case NAND_ECC_ON_DIE: 100 nand_dev->ecc.mode = NAND_ECC_ONDIE; 101 break; 102 103 default: 104 if (nand_dev->ecc.max_bit_corr == 0U) { 105 ERROR("No valid eccbit number\n"); 106 return -EINVAL; 107 } 108 } 109 } else { 110 /* Selected multiple plane NAND */ 111 if ((nand_param & NAND_PLANE_BIT_NB_MASK) != 0U) { 112 nand_dev->nb_planes = 2U; 113 } else { 114 nand_dev->nb_planes = 1U; 115 } 116 } 117 118 VERBOSE("OTP: Block %u Page %u Size %llu\n", nand_dev->block_size, 119 nand_dev->page_size, nand_dev->size); 120 121 return 0; 122 } 123 #endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */ 124 125 #if STM32MP_RAW_NAND 126 int plat_get_raw_nand_data(struct rawnand_device *device) 127 { 128 device->nand_dev->ecc.mode = NAND_ECC_HW; 129 device->nand_dev->ecc.size = SZ_512; 130 131 return get_data_from_otp(device->nand_dev, true); 132 } 133 #endif 134 135 #if STM32MP_SPI_NAND 136 int plat_get_spi_nand_data(struct spinand_device *device) 137 { 138 zeromem(&device->spi_read_cache_op, sizeof(struct spi_mem_op)); 139 device->spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE_4X; 140 device->spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 141 device->spi_read_cache_op.addr.nbytes = 2U; 142 device->spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 143 device->spi_read_cache_op.dummy.nbytes = 1U; 144 device->spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 145 device->spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE; 146 device->spi_read_cache_op.data.dir = SPI_MEM_DATA_IN; 147 148 return get_data_from_otp(device->nand_dev, false); 149 } 150 #endif 151 152 #if STM32MP_SPI_NOR 153 int plat_get_nor_data(struct nor_device *device) 154 { 155 device->size = SZ_64M; 156 157 zeromem(&device->read_op, sizeof(struct spi_mem_op)); 158 device->read_op.cmd.opcode = SPI_NOR_OP_READ_1_1_4; 159 device->read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 160 device->read_op.addr.nbytes = 3U; 161 device->read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 162 device->read_op.dummy.nbytes = 1U; 163 device->read_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 164 device->read_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE; 165 device->read_op.data.dir = SPI_MEM_DATA_IN; 166 167 return 0; 168 } 169 #endif 170