1 /* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/runtime_svc.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 16 #include <gpc.h> 17 #include <imx8m_psci.h> 18 #include <plat_imx8.h> 19 20 #define MAX_PLL_NUM U(10) 21 22 static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, }; 23 24 DEFINE_BAKERY_LOCK(gpc_lock); 25 26 #define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03 27 28 #pragma weak imx_set_cpu_pwr_off 29 #pragma weak imx_set_cpu_pwr_on 30 #pragma weak imx_set_cpu_lpm 31 #pragma weak imx_set_cluster_powerdown 32 33 void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint) 34 { 35 uint64_t temp_base; 36 37 temp_base = (uint64_t) sec_entrypoint; 38 temp_base >>= 2; 39 40 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3), 41 ((uint32_t)(temp_base >> 22) & 0xffff)); 42 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4, 43 ((uint32_t)temp_base & 0x003fffff)); 44 } 45 46 void imx_set_cpu_pwr_off(unsigned int core_id) 47 { 48 49 bakery_lock_get(&gpc_lock); 50 51 /* enable the wfi power down of the core */ 52 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); 53 54 bakery_lock_release(&gpc_lock); 55 56 /* assert the pcg pcr bit of the core */ 57 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 58 } 59 60 void imx_set_cpu_pwr_on(unsigned int core_id) 61 { 62 bakery_lock_get(&gpc_lock); 63 64 /* clear the wfi power down bit of the core */ 65 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); 66 67 bakery_lock_release(&gpc_lock); 68 69 /* assert the ncpuporeset */ 70 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); 71 /* assert the pcg pcr bit of the core */ 72 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 73 /* sw power up the core */ 74 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); 75 76 /* wait for the power up finished */ 77 while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0) 78 ; 79 80 /* deassert the pcg pcr bit of the core */ 81 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 82 /* deassert the ncpuporeset */ 83 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); 84 } 85 86 void imx_set_cpu_lpm(unsigned int core_id, bool pdn) 87 { 88 bakery_lock_get(&gpc_lock); 89 90 if (pdn) { 91 /* enable the core WFI PDN & IRQ PUP */ 92 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 93 COREx_IRQ_WUP(core_id)); 94 /* assert the pcg pcr bit of the core */ 95 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 96 } else { 97 /* disbale CORE WFI PDN & IRQ PUP */ 98 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 99 COREx_IRQ_WUP(core_id)); 100 /* deassert the pcg pcr bit of the core */ 101 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 102 } 103 104 bakery_lock_release(&gpc_lock); 105 } 106 107 /* 108 * the plat and noc can only be power up & down by slot method, 109 * slot0: plat power down; slot1: noc power down; slot2: noc power up; 110 * slot3: plat power up. plat's pup&pdn ack is used by default. if 111 * noc is config to power down, then noc's pdn ack should be used. 112 */ 113 static void imx_a53_plat_slot_config(bool pdn) 114 { 115 if (pdn) { 116 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); 117 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); 118 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_PLAT_PDN_ACK | 119 A53_PLAT_PUP_ACK); 120 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); 121 } else { 122 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); 123 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); 124 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK | 125 A53_DUMMY_PDN_ACK); 126 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); 127 } 128 } 129 130 void imx_set_cluster_standby(bool enter) 131 { 132 /* 133 * Enable BIT 6 of A53 AD register to make sure system 134 * don't enter LPM mode. 135 */ 136 if (enter) 137 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); 138 else 139 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); 140 } 141 142 /* i.mx8mq need to override it */ 143 void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state) 144 { 145 uint32_t val; 146 147 if (!is_local_state_run(power_state)) { 148 /* config C0~1's LPM, enable a53 clock off in LPM */ 149 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM, 150 LPM_MODE(power_state)); 151 /* config C2-3's LPM */ 152 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, LPM_MODE(power_state)); 153 154 /* enable PLAT/SCU power down */ 155 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); 156 val &= ~EN_L2_WFI_PDN; 157 /* L2 cache memory is on in WAIT mode */ 158 if (is_local_state_off(power_state)) { 159 val |= (L2PGE | EN_PLAT_PDN); 160 imx_a53_plat_slot_config(true); 161 } 162 163 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); 164 } else { 165 /* clear the slot and ack for cluster power down */ 166 imx_a53_plat_slot_config(false); 167 /* reverse the cluster level setting */ 168 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM); 169 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); 170 171 /* clear PLAT/SCU power down */ 172 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN), 173 EN_L2_WFI_PDN); 174 } 175 } 176 177 static unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) 178 { 179 unsigned int n = id >> ISENABLER_SHIFT; 180 181 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); 182 } 183 184 /* 185 * gic's clock will be gated in system suspend, so gic has no ability to 186 * to wakeup the system, we need to config the imr based on the irq 187 * enable status in gic, then gpc will monitor the wakeup irq 188 */ 189 void imx_set_sys_wakeup(unsigned int last_core, bool pdn) 190 { 191 uint32_t irq_mask; 192 uintptr_t gicd_base = PLAT_GICD_BASE; 193 194 if (pdn) 195 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core), 196 IRQ_SRC_A53_WUP); 197 else 198 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP, 199 A53_CORE_WUP_SRC(last_core)); 200 201 /* clear last core's IMR based on GIC's mask setting */ 202 for (int i = 0; i < IRQ_IMR_NUM; i++) { 203 if (pdn) 204 /* set the wakeup irq base GIC */ 205 irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1)); 206 else 207 irq_mask = IMR_MASK_ALL; 208 209 mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4, 210 irq_mask); 211 } 212 } 213 214 #pragma weak imx_noc_slot_config 215 /* 216 * this function only need to be override by platform 217 * that support noc power down, for example: imx8mm. 218 * otherwize, keep it empty. 219 */ 220 void imx_noc_slot_config(bool pdn) 221 { 222 223 } 224 225 /* this is common for all imx8m soc */ 226 void imx_set_sys_lpm(unsigned int last_core, bool retention) 227 { 228 uint32_t val; 229 230 val = mmio_read_32(IMX_GPC_BASE + SLPCR); 231 val &= ~(SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS | 232 SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE); 233 234 if (retention) 235 val |= (SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS | 236 SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE); 237 238 mmio_write_32(IMX_GPC_BASE + SLPCR, val); 239 240 /* config the noc power down */ 241 imx_noc_slot_config(retention); 242 243 /* config wakeup irqs' mask in gpc */ 244 imx_set_sys_wakeup(last_core, retention); 245 } 246 247 void imx_set_rbc_count(void) 248 { 249 mmio_setbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | 250 (0x8 << SLPCR_RBC_COUNT_SHIFT)); 251 } 252 253 void imx_clear_rbc_count(void) 254 { 255 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | 256 (0x3f << SLPCR_RBC_COUNT_SHIFT)); 257 } 258 259 struct pll_override { 260 uint32_t reg; 261 uint32_t override_mask; 262 }; 263 264 struct pll_override pll[MAX_PLL_NUM] = { 265 {.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), }, 266 {.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), }, 267 {.reg = 0x28, .override_mask = (1 << 12) | (1 << 8), }, 268 {.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), }, 269 {.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), }, 270 {.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), }, 271 {.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), }, 272 {.reg = 0x94, .override_mask = 0x5555500, }, 273 {.reg = 0x104, .override_mask = 0x5555500, }, 274 {.reg = 0x114, .override_mask = 0x500, }, 275 }; 276 277 #define PLL_BYPASS BIT(4) 278 void imx_anamix_override(bool enter) 279 { 280 unsigned int i; 281 282 /* 283 * bypass all the plls & enable the override bit before 284 * entering DSM mode. 285 */ 286 for (i = 0U; i < MAX_PLL_NUM; i++) { 287 if (enter) { 288 mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); 289 mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); 290 } else { 291 mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); 292 mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); 293 } 294 } 295 } 296 297 int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3) 298 { 299 switch (x1) { 300 case FSL_SIP_CONFIG_GPC_PM_DOMAIN: 301 imx_gpc_pm_domain_enable(x2, x3); 302 break; 303 default: 304 return SMC_UNK; 305 } 306 307 return 0; 308 } 309