1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/arm/gicv2.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 18 #include <plat_private.h> 19 #include "pm_api_sys.h" 20 #include "pm_client.h" 21 22 uintptr_t zynqmp_sec_entry; 23 24 void zynqmp_cpu_standby(plat_local_state_t cpu_state) 25 { 26 VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); 27 28 dsb(); 29 wfi(); 30 } 31 32 static int zynqmp_pwr_domain_on(u_register_t mpidr) 33 { 34 unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); 35 const struct pm_proc *proc; 36 uint32_t buff[3]; 37 enum pm_ret_status ret; 38 39 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); 40 41 if (cpu_id == -1) 42 return PSCI_E_INTERN_FAIL; 43 44 proc = pm_get_proc(cpu_id); 45 46 /* Check the APU proc status before wakeup */ 47 ret = pm_get_node_status(proc->node_id, buff); 48 if ((ret != PM_RET_SUCCESS) || (buff[0] == PM_PROC_STATE_SUSPENDING)) { 49 return PSCI_E_INTERN_FAIL; 50 } 51 52 /* Clear power down request */ 53 pm_client_wakeup(proc); 54 55 /* Send request to PMU to wake up selected APU CPU core */ 56 pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING); 57 58 return PSCI_E_SUCCESS; 59 } 60 61 static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state) 62 { 63 unsigned int cpu_id = plat_my_core_pos(); 64 const struct pm_proc *proc = pm_get_proc(cpu_id); 65 66 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) 67 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 68 __func__, i, target_state->pwr_domain_state[i]); 69 70 /* Prevent interrupts from spuriously waking up this cpu */ 71 gicv2_cpuif_disable(); 72 73 /* 74 * Send request to PMU to power down the appropriate APU CPU 75 * core. 76 * According to PSCI specification, CPU_off function does not 77 * have resume address and CPU core can only be woken up 78 * invoking CPU_on function, during which resume address will 79 * be set. 80 */ 81 pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0); 82 } 83 84 static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) 85 { 86 unsigned int state; 87 unsigned int cpu_id = plat_my_core_pos(); 88 const struct pm_proc *proc = pm_get_proc(cpu_id); 89 90 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) 91 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 92 __func__, i, target_state->pwr_domain_state[i]); 93 94 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? 95 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 96 97 /* Send request to PMU to suspend this core */ 98 pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry); 99 100 /* APU is to be turned off */ 101 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 102 /* disable coherency */ 103 plat_arm_interconnect_exit_coherency(); 104 } 105 } 106 107 static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) 108 { 109 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) 110 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 111 __func__, i, target_state->pwr_domain_state[i]); 112 plat_arm_gic_pcpu_init(); 113 gicv2_cpuif_enable(); 114 } 115 116 static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 117 { 118 unsigned int cpu_id = plat_my_core_pos(); 119 const struct pm_proc *proc = pm_get_proc(cpu_id); 120 121 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) 122 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 123 __func__, i, target_state->pwr_domain_state[i]); 124 125 /* Clear the APU power control register for this cpu */ 126 pm_client_wakeup(proc); 127 128 /* enable coherency */ 129 plat_arm_interconnect_enter_coherency(); 130 /* APU was turned off */ 131 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 132 plat_arm_gic_init(); 133 } else { 134 gicv2_cpuif_enable(); 135 gicv2_pcpu_distif_init(); 136 } 137 } 138 139 /******************************************************************************* 140 * ZynqMP handlers to shutdown/reboot the system 141 ******************************************************************************/ 142 143 static void __dead2 zynqmp_system_off(void) 144 { 145 /* disable coherency */ 146 plat_arm_interconnect_exit_coherency(); 147 148 /* Send the power down request to the PMU */ 149 pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN, 150 pm_get_shutdown_scope()); 151 152 while (1) 153 wfi(); 154 } 155 156 static void __dead2 zynqmp_system_reset(void) 157 { 158 /* disable coherency */ 159 plat_arm_interconnect_exit_coherency(); 160 161 /* Send the system reset request to the PMU */ 162 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, 163 pm_get_shutdown_scope()); 164 165 while (1) 166 wfi(); 167 } 168 169 int zynqmp_validate_power_state(unsigned int power_state, 170 psci_power_state_t *req_state) 171 { 172 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 173 174 int pstate = psci_get_pstate_type(power_state); 175 176 assert(req_state); 177 178 /* Sanity check the requested state */ 179 if (pstate == PSTATE_TYPE_STANDBY) 180 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 181 else 182 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 183 184 /* We expect the 'state id' to be zero */ 185 if (psci_get_pstate_id(power_state)) 186 return PSCI_E_INVALID_PARAMS; 187 188 return PSCI_E_SUCCESS; 189 } 190 191 void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) 192 { 193 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; 194 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; 195 } 196 197 /******************************************************************************* 198 * Export the platform handlers to enable psci to invoke them 199 ******************************************************************************/ 200 static const struct plat_psci_ops zynqmp_psci_ops = { 201 .cpu_standby = zynqmp_cpu_standby, 202 .pwr_domain_on = zynqmp_pwr_domain_on, 203 .pwr_domain_off = zynqmp_pwr_domain_off, 204 .pwr_domain_suspend = zynqmp_pwr_domain_suspend, 205 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, 206 .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, 207 .system_off = zynqmp_system_off, 208 .system_reset = zynqmp_system_reset, 209 .validate_power_state = zynqmp_validate_power_state, 210 .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, 211 }; 212 213 /******************************************************************************* 214 * Export the platform specific power ops. 215 ******************************************************************************/ 216 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 217 const struct plat_psci_ops **psci_ops) 218 { 219 zynqmp_sec_entry = sec_entrypoint; 220 221 *psci_ops = &zynqmp_psci_ops; 222 223 return 0; 224 } 225