1 /* 2 * Copyright (c) 2020-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_N2_H 8 #define NEOVERSE_N2_H 9 10 /* Neoverse N2 ID register for revision r0p0 */ 11 #define NEOVERSE_N2_MIDR U(0x410FD490) 12 13 /* Neoverse N2 loop count for CVE-2022-23960 mitigation */ 14 #define NEOVERSE_N2_BHB_LOOP_COUNT U(32) 15 16 /******************************************************************************* 17 * CPU Power control register 18 ******************************************************************************/ 19 #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 20 #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) 21 22 /******************************************************************************* 23 * CPU Extended Control register specific definitions. 24 ******************************************************************************/ 25 #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 26 #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 27 #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 28 29 /******************************************************************************* 30 * CPU Auxiliary Control register specific definitions. 31 ******************************************************************************/ 32 #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 33 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 34 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 35 36 /******************************************************************************* 37 * CPU Auxiliary Control register 2 specific definitions. 38 ******************************************************************************/ 39 #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 40 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 41 42 /******************************************************************************* 43 * CPU Auxiliary Control register 5 specific definitions. 44 ******************************************************************************/ 45 #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 46 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 47 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) 48 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 49 50 /******************************************************************************* 51 * CPU Auxiliary Control register specific definitions. 52 ******************************************************************************/ 53 #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 54 #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 55 #define CPUECTLR2_EL1_PF_MODE_LSB U(11) 56 #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 57 58 #endif /* NEOVERSE_N2_H */ 59