1 /* 2 * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <arch_helpers.h> 14 #include <arch/aarch64/arch_features.h> 15 #include <bl31/bl31.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/debug.h> 18 #include <common/runtime_svc.h> 19 #include <common/tbbr/tbbr_img_def.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/fconf/fconf.h> 22 #include <lib/fconf/fconf_dyn_cfg_getter.h> 23 #include <lib/smccc.h> 24 #include <lib/spinlock.h> 25 #include <lib/utils.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 #include <plat/common/common_def.h> 28 #include <plat/common/platform.h> 29 #include <platform_def.h> 30 #include <services/ffa_svc.h> 31 #include <services/spmc_svc.h> 32 #include <services/spmd_svc.h> 33 #include <smccc_helpers.h> 34 #include "spmd_private.h" 35 36 /******************************************************************************* 37 * SPM Core context information. 38 ******************************************************************************/ 39 static spmd_spm_core_context_t spm_core_context[PLATFORM_CORE_COUNT]; 40 41 /******************************************************************************* 42 * SPM Core attribute information is read from its manifest if the SPMC is not 43 * at EL3. Else, it is populated from the SPMC directly. 44 ******************************************************************************/ 45 static spmc_manifest_attribute_t spmc_attrs; 46 47 /******************************************************************************* 48 * SPM Core entry point information. Discovered on the primary core and reused 49 * on secondary cores. 50 ******************************************************************************/ 51 static entry_point_info_t *spmc_ep_info; 52 53 /******************************************************************************* 54 * SPM Core context on CPU based on mpidr. 55 ******************************************************************************/ 56 spmd_spm_core_context_t *spmd_get_context_by_mpidr(uint64_t mpidr) 57 { 58 int core_idx = plat_core_pos_by_mpidr(mpidr); 59 60 if (core_idx < 0) { 61 ERROR("Invalid mpidr: %" PRIx64 ", returned ID: %d\n", mpidr, core_idx); 62 panic(); 63 } 64 65 return &spm_core_context[core_idx]; 66 } 67 68 /******************************************************************************* 69 * SPM Core context on current CPU get helper. 70 ******************************************************************************/ 71 spmd_spm_core_context_t *spmd_get_context(void) 72 { 73 return spmd_get_context_by_mpidr(read_mpidr()); 74 } 75 76 /******************************************************************************* 77 * SPM Core ID getter. 78 ******************************************************************************/ 79 uint16_t spmd_spmc_id_get(void) 80 { 81 return spmc_attrs.spmc_id; 82 } 83 84 /******************************************************************************* 85 * Static function declaration. 86 ******************************************************************************/ 87 static int32_t spmd_init(void); 88 static int spmd_spmc_init(void *pm_addr); 89 static uint64_t spmd_ffa_error_return(void *handle, 90 int error_code); 91 static uint64_t spmd_smc_forward(uint32_t smc_fid, 92 bool secure_origin, 93 uint64_t x1, 94 uint64_t x2, 95 uint64_t x3, 96 uint64_t x4, 97 void *cookie, 98 void *handle, 99 uint64_t flags); 100 101 /****************************************************************************** 102 * Builds an SPMD to SPMC direct message request. 103 *****************************************************************************/ 104 void spmd_build_spmc_message(gp_regs_t *gpregs, uint8_t target_func, 105 unsigned long long message) 106 { 107 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); 108 write_ctx_reg(gpregs, CTX_GPREG_X1, 109 (SPMD_DIRECT_MSG_ENDPOINT_ID << FFA_DIRECT_MSG_SOURCE_SHIFT) | 110 spmd_spmc_id_get()); 111 write_ctx_reg(gpregs, CTX_GPREG_X2, BIT(31) | target_func); 112 write_ctx_reg(gpregs, CTX_GPREG_X3, message); 113 } 114 115 116 /******************************************************************************* 117 * This function takes an SPMC context pointer and performs a synchronous 118 * SPMC entry. 119 ******************************************************************************/ 120 uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *spmc_ctx) 121 { 122 uint64_t rc; 123 124 assert(spmc_ctx != NULL); 125 126 cm_set_context(&(spmc_ctx->cpu_ctx), SECURE); 127 128 /* Restore the context assigned above */ 129 #if SPMD_SPM_AT_SEL2 130 cm_el2_sysregs_context_restore(SECURE); 131 #else 132 cm_el1_sysregs_context_restore(SECURE); 133 #endif 134 cm_set_next_eret_context(SECURE); 135 136 /* Enter SPMC */ 137 rc = spmd_spm_core_enter(&spmc_ctx->c_rt_ctx); 138 139 /* Save secure state */ 140 #if SPMD_SPM_AT_SEL2 141 cm_el2_sysregs_context_save(SECURE); 142 #else 143 cm_el1_sysregs_context_save(SECURE); 144 #endif 145 146 return rc; 147 } 148 149 /******************************************************************************* 150 * This function returns to the place where spmd_spm_core_sync_entry() was 151 * called originally. 152 ******************************************************************************/ 153 __dead2 void spmd_spm_core_sync_exit(uint64_t rc) 154 { 155 spmd_spm_core_context_t *ctx = spmd_get_context(); 156 157 /* Get current CPU context from SPMC context */ 158 assert(cm_get_context(SECURE) == &(ctx->cpu_ctx)); 159 160 /* 161 * The SPMD must have initiated the original request through a 162 * synchronous entry into SPMC. Jump back to the original C runtime 163 * context with the value of rc in x0; 164 */ 165 spmd_spm_core_exit(ctx->c_rt_ctx, rc); 166 167 panic(); 168 } 169 170 /******************************************************************************* 171 * Jump to the SPM Core for the first time. 172 ******************************************************************************/ 173 static int32_t spmd_init(void) 174 { 175 spmd_spm_core_context_t *ctx = spmd_get_context(); 176 uint64_t rc; 177 178 VERBOSE("SPM Core init start.\n"); 179 180 /* Primary boot core enters the SPMC for initialization. */ 181 ctx->state = SPMC_STATE_ON_PENDING; 182 183 rc = spmd_spm_core_sync_entry(ctx); 184 if (rc != 0ULL) { 185 ERROR("SPMC initialisation failed 0x%" PRIx64 "\n", rc); 186 return 0; 187 } 188 189 ctx->state = SPMC_STATE_ON; 190 191 VERBOSE("SPM Core init end.\n"); 192 193 return 1; 194 } 195 196 /******************************************************************************* 197 * spmd_secure_interrupt_handler 198 * Enter the SPMC for further handling of the secure interrupt by the SPMC 199 * itself or a Secure Partition. 200 ******************************************************************************/ 201 static uint64_t spmd_secure_interrupt_handler(uint32_t id, 202 uint32_t flags, 203 void *handle, 204 void *cookie) 205 { 206 spmd_spm_core_context_t *ctx = spmd_get_context(); 207 gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx); 208 unsigned int linear_id = plat_my_core_pos(); 209 int64_t rc; 210 211 /* Sanity check the security state when the exception was generated */ 212 assert(get_interrupt_src_ss(flags) == NON_SECURE); 213 214 /* Sanity check the pointer to this cpu's context */ 215 assert(handle == cm_get_context(NON_SECURE)); 216 217 /* Save the non-secure context before entering SPMC */ 218 cm_el1_sysregs_context_save(NON_SECURE); 219 #if SPMD_SPM_AT_SEL2 220 cm_el2_sysregs_context_save(NON_SECURE); 221 #endif 222 223 /* Convey the event to the SPMC through the FFA_INTERRUPT interface. */ 224 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_INTERRUPT); 225 write_ctx_reg(gpregs, CTX_GPREG_X1, 0); 226 write_ctx_reg(gpregs, CTX_GPREG_X2, 0); 227 write_ctx_reg(gpregs, CTX_GPREG_X3, 0); 228 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); 229 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); 230 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); 231 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); 232 233 /* Mark current core as handling a secure interrupt. */ 234 ctx->secure_interrupt_ongoing = true; 235 236 rc = spmd_spm_core_sync_entry(ctx); 237 if (rc != 0ULL) { 238 ERROR("%s failed (%" PRId64 ") on CPU%u\n", __func__, rc, linear_id); 239 } 240 241 ctx->secure_interrupt_ongoing = false; 242 243 cm_el1_sysregs_context_restore(NON_SECURE); 244 #if SPMD_SPM_AT_SEL2 245 cm_el2_sysregs_context_restore(NON_SECURE); 246 #endif 247 cm_set_next_eret_context(NON_SECURE); 248 249 SMC_RET0(&ctx->cpu_ctx); 250 } 251 252 /******************************************************************************* 253 * spmd_group0_interrupt_handler_nwd 254 * Group0 secure interrupt in the normal world are trapped to EL3. Delegate the 255 * handling of the interrupt to the platform handler, and return only upon 256 * successfully handling the Group0 interrupt. 257 ******************************************************************************/ 258 static uint64_t spmd_group0_interrupt_handler_nwd(uint32_t id, 259 uint32_t flags, 260 void *handle, 261 void *cookie) 262 { 263 uint32_t intid; 264 265 /* Sanity check the security state when the exception was generated. */ 266 assert(get_interrupt_src_ss(flags) == NON_SECURE); 267 268 /* Sanity check the pointer to this cpu's context. */ 269 assert(handle == cm_get_context(NON_SECURE)); 270 271 assert(id == INTR_ID_UNAVAILABLE); 272 273 assert(plat_ic_get_pending_interrupt_type() == INTR_TYPE_EL3); 274 275 intid = plat_ic_get_pending_interrupt_id(); 276 277 if (plat_spmd_handle_group0_interrupt(intid) < 0) { 278 ERROR("Group0 interrupt %u not handled\n", intid); 279 panic(); 280 } 281 282 return 0U; 283 } 284 285 /******************************************************************************* 286 * spmd_handle_group0_intr_swd 287 * SPMC delegates handling of Group0 secure interrupt to EL3 firmware using 288 * FFA_EL3_INTR_HANDLE SMC call. Further, SPMD delegates the handling of the 289 * interrupt to the platform handler, and returns only upon successfully 290 * handling the Group0 interrupt. 291 ******************************************************************************/ 292 static uint64_t spmd_handle_group0_intr_swd(void *handle) 293 { 294 uint32_t intid; 295 296 /* Sanity check the pointer to this cpu's context */ 297 assert(handle == cm_get_context(SECURE)); 298 299 assert(plat_ic_get_pending_interrupt_type() == INTR_TYPE_EL3); 300 301 intid = plat_ic_get_pending_interrupt_id(); 302 303 /* 304 * TODO: Currently due to a limitation in SPMD implementation, the 305 * platform handler is expected to not delegate handling to NWd while 306 * processing Group0 secure interrupt. 307 */ 308 if (plat_spmd_handle_group0_interrupt(intid) < 0) { 309 /* Group0 interrupt was not handled by the platform. */ 310 ERROR("Group0 interrupt %u not handled\n", intid); 311 panic(); 312 } 313 314 /* Return success. */ 315 SMC_RET8(handle, FFA_SUCCESS_SMC32, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 316 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 317 FFA_PARAM_MBZ); 318 } 319 320 #if ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 321 static int spmd_dynamic_map_mem(uintptr_t base_addr, size_t size, 322 unsigned int attr, uintptr_t *align_addr, 323 size_t *align_size) 324 { 325 uintptr_t base_addr_align; 326 size_t mapped_size_align; 327 int rc; 328 329 /* Page aligned address and size if necessary */ 330 base_addr_align = page_align(base_addr, DOWN); 331 mapped_size_align = page_align(size, UP); 332 333 if ((base_addr != base_addr_align) && 334 (size == mapped_size_align)) { 335 mapped_size_align += PAGE_SIZE; 336 } 337 338 /* 339 * Map dynamically given region with its aligned base address and 340 * size 341 */ 342 rc = mmap_add_dynamic_region((unsigned long long)base_addr_align, 343 base_addr_align, 344 mapped_size_align, 345 attr); 346 if (rc == 0) { 347 *align_addr = base_addr_align; 348 *align_size = mapped_size_align; 349 } 350 351 return rc; 352 } 353 354 static void spmd_do_sec_cpy(uintptr_t root_base_addr, uintptr_t sec_base_addr, 355 size_t size) 356 { 357 uintptr_t root_base_addr_align, sec_base_addr_align; 358 size_t root_mapped_size_align, sec_mapped_size_align; 359 int rc; 360 361 assert(root_base_addr != 0UL); 362 assert(sec_base_addr != 0UL); 363 assert(size != 0UL); 364 365 /* Map the memory with required attributes */ 366 rc = spmd_dynamic_map_mem(root_base_addr, size, MT_RO_DATA | MT_ROOT, 367 &root_base_addr_align, 368 &root_mapped_size_align); 369 if (rc != 0) { 370 ERROR("%s %s %lu (%d)\n", "Error while mapping", "root region", 371 root_base_addr, rc); 372 panic(); 373 } 374 375 rc = spmd_dynamic_map_mem(sec_base_addr, size, MT_RW_DATA | MT_SECURE, 376 &sec_base_addr_align, &sec_mapped_size_align); 377 if (rc != 0) { 378 ERROR("%s %s %lu (%d)\n", "Error while mapping", 379 "secure region", sec_base_addr, rc); 380 panic(); 381 } 382 383 /* Do copy operation */ 384 (void)memcpy((void *)sec_base_addr, (void *)root_base_addr, size); 385 386 /* Unmap root memory region */ 387 rc = mmap_remove_dynamic_region(root_base_addr_align, 388 root_mapped_size_align); 389 if (rc != 0) { 390 ERROR("%s %s %lu (%d)\n", "Error while unmapping", 391 "root region", root_base_addr_align, rc); 392 panic(); 393 } 394 395 /* Unmap secure memory region */ 396 rc = mmap_remove_dynamic_region(sec_base_addr_align, 397 sec_mapped_size_align); 398 if (rc != 0) { 399 ERROR("%s %s %lu (%d)\n", "Error while unmapping", 400 "secure region", sec_base_addr_align, rc); 401 panic(); 402 } 403 } 404 #endif /* ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */ 405 406 /******************************************************************************* 407 * Loads SPMC manifest and inits SPMC. 408 ******************************************************************************/ 409 static int spmd_spmc_init(void *pm_addr) 410 { 411 cpu_context_t *cpu_ctx; 412 unsigned int core_id; 413 uint32_t ep_attr, flags; 414 int rc; 415 const struct dyn_cfg_dtb_info_t *image_info __unused; 416 417 /* Load the SPM Core manifest */ 418 rc = plat_spm_core_manifest_load(&spmc_attrs, pm_addr); 419 if (rc != 0) { 420 WARN("No or invalid SPM Core manifest image provided by BL2\n"); 421 return rc; 422 } 423 424 /* 425 * Ensure that the SPM Core version is compatible with the SPM 426 * Dispatcher version. 427 */ 428 if ((spmc_attrs.major_version != FFA_VERSION_MAJOR) || 429 (spmc_attrs.minor_version > FFA_VERSION_MINOR)) { 430 WARN("Unsupported FFA version (%u.%u)\n", 431 spmc_attrs.major_version, spmc_attrs.minor_version); 432 return -EINVAL; 433 } 434 435 VERBOSE("FFA version (%u.%u)\n", spmc_attrs.major_version, 436 spmc_attrs.minor_version); 437 438 VERBOSE("SPM Core run time EL%x.\n", 439 SPMD_SPM_AT_SEL2 ? MODE_EL2 : MODE_EL1); 440 441 /* Validate the SPMC ID, Ensure high bit is set */ 442 if (((spmc_attrs.spmc_id >> SPMC_SECURE_ID_SHIFT) & 443 SPMC_SECURE_ID_MASK) == 0U) { 444 WARN("Invalid ID (0x%x) for SPMC.\n", spmc_attrs.spmc_id); 445 return -EINVAL; 446 } 447 448 /* Validate the SPM Core execution state */ 449 if ((spmc_attrs.exec_state != MODE_RW_64) && 450 (spmc_attrs.exec_state != MODE_RW_32)) { 451 WARN("Unsupported %s%x.\n", "SPM Core execution state 0x", 452 spmc_attrs.exec_state); 453 return -EINVAL; 454 } 455 456 VERBOSE("%s%x.\n", "SPM Core execution state 0x", 457 spmc_attrs.exec_state); 458 459 #if SPMD_SPM_AT_SEL2 460 /* Ensure manifest has not requested AArch32 state in S-EL2 */ 461 if (spmc_attrs.exec_state == MODE_RW_32) { 462 WARN("AArch32 state at S-EL2 is not supported.\n"); 463 return -EINVAL; 464 } 465 466 /* 467 * Check if S-EL2 is supported on this system if S-EL2 468 * is required for SPM 469 */ 470 if (!is_feat_sel2_supported()) { 471 WARN("SPM Core run time S-EL2 is not supported.\n"); 472 return -EINVAL; 473 } 474 #endif /* SPMD_SPM_AT_SEL2 */ 475 476 /* Initialise an entrypoint to set up the CPU context */ 477 ep_attr = SECURE | EP_ST_ENABLE; 478 if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0ULL) { 479 ep_attr |= EP_EE_BIG; 480 } 481 482 SET_PARAM_HEAD(spmc_ep_info, PARAM_EP, VERSION_1, ep_attr); 483 484 /* 485 * Populate SPSR for SPM Core based upon validated parameters from the 486 * manifest. 487 */ 488 if (spmc_attrs.exec_state == MODE_RW_32) { 489 spmc_ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, 490 SPSR_E_LITTLE, 491 DAIF_FIQ_BIT | 492 DAIF_IRQ_BIT | 493 DAIF_ABT_BIT); 494 } else { 495 496 #if SPMD_SPM_AT_SEL2 497 static const uint32_t runtime_el = MODE_EL2; 498 #else 499 static const uint32_t runtime_el = MODE_EL1; 500 #endif 501 spmc_ep_info->spsr = SPSR_64(runtime_el, 502 MODE_SP_ELX, 503 DISABLE_ALL_EXCEPTIONS); 504 } 505 506 #if ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 507 image_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TOS_FW_CONFIG_ID); 508 assert(image_info != NULL); 509 510 if ((image_info->config_addr == 0UL) || 511 (image_info->secondary_config_addr == 0UL) || 512 (image_info->config_max_size == 0UL)) { 513 return -EINVAL; 514 } 515 516 /* Copy manifest from root->secure region */ 517 spmd_do_sec_cpy(image_info->config_addr, 518 image_info->secondary_config_addr, 519 image_info->config_max_size); 520 521 /* Update ep info of BL32 */ 522 assert(spmc_ep_info != NULL); 523 spmc_ep_info->args.arg0 = image_info->secondary_config_addr; 524 #endif /* ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */ 525 526 /* Set an initial SPMC context state for all cores. */ 527 for (core_id = 0U; core_id < PLATFORM_CORE_COUNT; core_id++) { 528 spm_core_context[core_id].state = SPMC_STATE_OFF; 529 530 /* Setup an initial cpu context for the SPMC. */ 531 cpu_ctx = &spm_core_context[core_id].cpu_ctx; 532 cm_setup_context(cpu_ctx, spmc_ep_info); 533 534 /* 535 * Pass the core linear ID to the SPMC through x4. 536 * (TF-A implementation defined behavior helping 537 * a legacy TOS migration to adopt FF-A). 538 */ 539 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4, core_id); 540 } 541 542 /* Register power management hooks with PSCI */ 543 psci_register_spd_pm_hook(&spmd_pm); 544 545 /* Register init function for deferred init. */ 546 bl31_register_bl32_init(&spmd_init); 547 548 INFO("SPM Core setup done.\n"); 549 550 /* 551 * Register an interrupt handler routing secure interrupts to SPMD 552 * while the NWd is running. 553 */ 554 flags = 0; 555 set_interrupt_rm_flag(flags, NON_SECURE); 556 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 557 spmd_secure_interrupt_handler, 558 flags); 559 if (rc != 0) { 560 panic(); 561 } 562 563 /* 564 * Register an interrupt handler routing Group0 interrupts to SPMD 565 * while the NWd is running. 566 */ 567 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 568 spmd_group0_interrupt_handler_nwd, 569 flags); 570 if (rc != 0) { 571 panic(); 572 } 573 return 0; 574 } 575 576 /******************************************************************************* 577 * Initialize context of SPM Core. 578 ******************************************************************************/ 579 int spmd_setup(void) 580 { 581 int rc; 582 void *spmc_manifest; 583 584 /* 585 * If the SPMC is at EL3, then just initialise it directly. The 586 * shenanigans of when it is at a lower EL are not needed. 587 */ 588 if (is_spmc_at_el3()) { 589 /* Allow the SPMC to populate its attributes directly. */ 590 spmc_populate_attrs(&spmc_attrs); 591 592 rc = spmc_setup(); 593 if (rc != 0) { 594 WARN("SPMC initialisation failed 0x%x.\n", rc); 595 } 596 return 0; 597 } 598 599 spmc_ep_info = bl31_plat_get_next_image_ep_info(SECURE); 600 if (spmc_ep_info == NULL) { 601 WARN("No SPM Core image provided by BL2 boot loader.\n"); 602 return 0; 603 } 604 605 /* Under no circumstances will this parameter be 0 */ 606 assert(spmc_ep_info->pc != 0ULL); 607 608 /* 609 * Check if BL32 ep_info has a reference to 'tos_fw_config'. This will 610 * be used as a manifest for the SPM Core at the next lower EL/mode. 611 */ 612 spmc_manifest = (void *)spmc_ep_info->args.arg0; 613 if (spmc_manifest == NULL) { 614 WARN("Invalid or absent SPM Core manifest.\n"); 615 return 0; 616 } 617 618 /* Load manifest, init SPMC */ 619 rc = spmd_spmc_init(spmc_manifest); 620 if (rc != 0) { 621 WARN("Booting device without SPM initialization.\n"); 622 } 623 624 return 0; 625 } 626 627 /******************************************************************************* 628 * Forward FF-A SMCs to the other security state. 629 ******************************************************************************/ 630 uint64_t spmd_smc_switch_state(uint32_t smc_fid, 631 bool secure_origin, 632 uint64_t x1, 633 uint64_t x2, 634 uint64_t x3, 635 uint64_t x4, 636 void *handle) 637 { 638 unsigned int secure_state_in = (secure_origin) ? SECURE : NON_SECURE; 639 unsigned int secure_state_out = (!secure_origin) ? SECURE : NON_SECURE; 640 641 /* Save incoming security state */ 642 #if SPMD_SPM_AT_SEL2 643 if (secure_state_in == NON_SECURE) { 644 cm_el1_sysregs_context_save(secure_state_in); 645 } 646 cm_el2_sysregs_context_save(secure_state_in); 647 #else 648 cm_el1_sysregs_context_save(secure_state_in); 649 #endif 650 651 /* Restore outgoing security state */ 652 #if SPMD_SPM_AT_SEL2 653 if (secure_state_out == NON_SECURE) { 654 cm_el1_sysregs_context_restore(secure_state_out); 655 } 656 cm_el2_sysregs_context_restore(secure_state_out); 657 #else 658 cm_el1_sysregs_context_restore(secure_state_out); 659 #endif 660 cm_set_next_eret_context(secure_state_out); 661 662 #if SPMD_SPM_AT_SEL2 663 /* 664 * If SPMC is at SEL2, save additional registers x8-x17, which may 665 * be used in FF-A calls such as FFA_PARTITION_INFO_GET_REGS. 666 * Note that technically, all SPMCs can support this, but this code is 667 * under ifdef to minimize breakage in case other SPMCs do not save 668 * and restore x8-x17. 669 * We also need to pass through these registers since not all FF-A ABIs 670 * modify x8-x17, in which case, SMCCC requires that these registers be 671 * preserved, so the SPMD passes through these registers and expects the 672 * SPMC to save and restore (potentially also modify) them. 673 */ 674 SMC_RET18(cm_get_context(secure_state_out), smc_fid, x1, x2, x3, x4, 675 SMC_GET_GP(handle, CTX_GPREG_X5), 676 SMC_GET_GP(handle, CTX_GPREG_X6), 677 SMC_GET_GP(handle, CTX_GPREG_X7), 678 SMC_GET_GP(handle, CTX_GPREG_X8), 679 SMC_GET_GP(handle, CTX_GPREG_X9), 680 SMC_GET_GP(handle, CTX_GPREG_X10), 681 SMC_GET_GP(handle, CTX_GPREG_X11), 682 SMC_GET_GP(handle, CTX_GPREG_X12), 683 SMC_GET_GP(handle, CTX_GPREG_X13), 684 SMC_GET_GP(handle, CTX_GPREG_X14), 685 SMC_GET_GP(handle, CTX_GPREG_X15), 686 SMC_GET_GP(handle, CTX_GPREG_X16), 687 SMC_GET_GP(handle, CTX_GPREG_X17) 688 ); 689 690 #else 691 SMC_RET8(cm_get_context(secure_state_out), smc_fid, x1, x2, x3, x4, 692 SMC_GET_GP(handle, CTX_GPREG_X5), 693 SMC_GET_GP(handle, CTX_GPREG_X6), 694 SMC_GET_GP(handle, CTX_GPREG_X7)); 695 #endif 696 } 697 698 /******************************************************************************* 699 * Forward SMCs to the other security state. 700 ******************************************************************************/ 701 static uint64_t spmd_smc_forward(uint32_t smc_fid, 702 bool secure_origin, 703 uint64_t x1, 704 uint64_t x2, 705 uint64_t x3, 706 uint64_t x4, 707 void *cookie, 708 void *handle, 709 uint64_t flags) 710 { 711 if (is_spmc_at_el3() && !secure_origin) { 712 return spmc_smc_handler(smc_fid, secure_origin, x1, x2, x3, x4, 713 cookie, handle, flags); 714 } 715 return spmd_smc_switch_state(smc_fid, secure_origin, x1, x2, x3, x4, 716 handle); 717 718 } 719 720 /******************************************************************************* 721 * Return FFA_ERROR with specified error code 722 ******************************************************************************/ 723 static uint64_t spmd_ffa_error_return(void *handle, int error_code) 724 { 725 SMC_RET8(handle, (uint32_t) FFA_ERROR, 726 FFA_TARGET_INFO_MBZ, (uint32_t)error_code, 727 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 728 FFA_PARAM_MBZ, FFA_PARAM_MBZ); 729 } 730 731 /******************************************************************************* 732 * spmd_check_address_in_binary_image 733 ******************************************************************************/ 734 bool spmd_check_address_in_binary_image(uint64_t address) 735 { 736 assert(!check_uptr_overflow(spmc_attrs.load_address, spmc_attrs.binary_size)); 737 738 return ((address >= spmc_attrs.load_address) && 739 (address < (spmc_attrs.load_address + spmc_attrs.binary_size))); 740 } 741 742 /****************************************************************************** 743 * spmd_is_spmc_message 744 *****************************************************************************/ 745 static bool spmd_is_spmc_message(unsigned int ep) 746 { 747 if (is_spmc_at_el3()) { 748 return false; 749 } 750 751 return ((ffa_endpoint_destination(ep) == SPMD_DIRECT_MSG_ENDPOINT_ID) 752 && (ffa_endpoint_source(ep) == spmc_attrs.spmc_id)); 753 } 754 755 /****************************************************************************** 756 * spmd_handle_spmc_message 757 *****************************************************************************/ 758 static int spmd_handle_spmc_message(unsigned long long msg, 759 unsigned long long parm1, unsigned long long parm2, 760 unsigned long long parm3, unsigned long long parm4) 761 { 762 VERBOSE("%s %llx %llx %llx %llx %llx\n", __func__, 763 msg, parm1, parm2, parm3, parm4); 764 765 return -EINVAL; 766 } 767 768 /******************************************************************************* 769 * This function forwards FF-A SMCs to either the main SPMD handler or the 770 * SPMC at EL3, depending on the origin security state, if enabled. 771 ******************************************************************************/ 772 uint64_t spmd_ffa_smc_handler(uint32_t smc_fid, 773 uint64_t x1, 774 uint64_t x2, 775 uint64_t x3, 776 uint64_t x4, 777 void *cookie, 778 void *handle, 779 uint64_t flags) 780 { 781 if (is_spmc_at_el3()) { 782 /* 783 * If we have an SPMC at EL3 allow handling of the SMC first. 784 * The SPMC will call back through to SPMD handler if required. 785 */ 786 if (is_caller_secure(flags)) { 787 return spmc_smc_handler(smc_fid, 788 is_caller_secure(flags), 789 x1, x2, x3, x4, cookie, 790 handle, flags); 791 } 792 } 793 return spmd_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 794 handle, flags); 795 } 796 797 /******************************************************************************* 798 * This function handles all SMCs in the range reserved for FFA. Each call is 799 * either forwarded to the other security state or handled by the SPM dispatcher 800 ******************************************************************************/ 801 uint64_t spmd_smc_handler(uint32_t smc_fid, 802 uint64_t x1, 803 uint64_t x2, 804 uint64_t x3, 805 uint64_t x4, 806 void *cookie, 807 void *handle, 808 uint64_t flags) 809 { 810 unsigned int linear_id = plat_my_core_pos(); 811 spmd_spm_core_context_t *ctx = spmd_get_context(); 812 bool secure_origin; 813 int32_t ret; 814 uint32_t input_version; 815 816 /* Determine which security state this SMC originated from */ 817 secure_origin = is_caller_secure(flags); 818 819 VERBOSE("SPM(%u): 0x%x 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 820 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 "\n", 821 linear_id, smc_fid, x1, x2, x3, x4, 822 SMC_GET_GP(handle, CTX_GPREG_X5), 823 SMC_GET_GP(handle, CTX_GPREG_X6), 824 SMC_GET_GP(handle, CTX_GPREG_X7)); 825 826 switch (smc_fid) { 827 case FFA_ERROR: 828 /* 829 * Check if this is the first invocation of this interface on 830 * this CPU. If so, then indicate that the SPM Core initialised 831 * unsuccessfully. 832 */ 833 if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) { 834 spmd_spm_core_sync_exit(x2); 835 } 836 837 return spmd_smc_forward(smc_fid, secure_origin, 838 x1, x2, x3, x4, cookie, 839 handle, flags); 840 break; /* not reached */ 841 842 case FFA_VERSION: 843 input_version = (uint32_t)(0xFFFFFFFF & x1); 844 /* 845 * If caller is secure and SPMC was initialized, 846 * return FFA_VERSION of SPMD. 847 * If caller is non secure and SPMC was initialized, 848 * forward to the EL3 SPMC if enabled, otherwise return 849 * the SPMC version if implemented at a lower EL. 850 * Sanity check to "input_version". 851 * If the EL3 SPMC is enabled, ignore the SPMC state as 852 * this is not used. 853 */ 854 if ((input_version & FFA_VERSION_BIT31_MASK) || 855 (!is_spmc_at_el3() && (ctx->state == SPMC_STATE_RESET))) { 856 ret = FFA_ERROR_NOT_SUPPORTED; 857 } else if (!secure_origin) { 858 if (is_spmc_at_el3()) { 859 /* 860 * Forward the call directly to the EL3 SPMC, if 861 * enabled, as we don't need to wrap the call in 862 * a direct request. 863 */ 864 return spmd_smc_forward(smc_fid, secure_origin, 865 x1, x2, x3, x4, cookie, 866 handle, flags); 867 } 868 869 gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx); 870 uint64_t rc; 871 872 if (spmc_attrs.major_version == 1 && 873 spmc_attrs.minor_version == 0) { 874 ret = MAKE_FFA_VERSION(spmc_attrs.major_version, 875 spmc_attrs.minor_version); 876 SMC_RET8(handle, (uint32_t)ret, 877 FFA_TARGET_INFO_MBZ, 878 FFA_TARGET_INFO_MBZ, 879 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 880 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 881 FFA_PARAM_MBZ); 882 break; 883 } 884 /* Save non-secure system registers context */ 885 cm_el1_sysregs_context_save(NON_SECURE); 886 #if SPMD_SPM_AT_SEL2 887 cm_el2_sysregs_context_save(NON_SECURE); 888 #endif 889 890 /* 891 * The incoming request has FFA_VERSION as X0 smc_fid 892 * and requested version in x1. Prepare a direct request 893 * from SPMD to SPMC with FFA_VERSION framework function 894 * identifier in X2 and requested version in X3. 895 */ 896 spmd_build_spmc_message(gpregs, 897 SPMD_FWK_MSG_FFA_VERSION_REQ, 898 input_version); 899 900 rc = spmd_spm_core_sync_entry(ctx); 901 902 if ((rc != 0ULL) || 903 (SMC_GET_GP(gpregs, CTX_GPREG_X0) != 904 FFA_MSG_SEND_DIRECT_RESP_SMC32) || 905 (SMC_GET_GP(gpregs, CTX_GPREG_X2) != 906 (FFA_FWK_MSG_BIT | 907 SPMD_FWK_MSG_FFA_VERSION_RESP))) { 908 ERROR("Failed to forward FFA_VERSION\n"); 909 ret = FFA_ERROR_NOT_SUPPORTED; 910 } else { 911 ret = SMC_GET_GP(gpregs, CTX_GPREG_X3); 912 } 913 914 /* 915 * Return here after SPMC has handled FFA_VERSION. 916 * The returned SPMC version is held in X3. 917 * Forward this version in X0 to the non-secure caller. 918 */ 919 return spmd_smc_forward(ret, true, FFA_PARAM_MBZ, 920 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 921 FFA_PARAM_MBZ, cookie, gpregs, 922 flags); 923 } else { 924 ret = MAKE_FFA_VERSION(FFA_VERSION_MAJOR, 925 FFA_VERSION_MINOR); 926 } 927 928 SMC_RET8(handle, (uint32_t)ret, FFA_TARGET_INFO_MBZ, 929 FFA_TARGET_INFO_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 930 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ); 931 break; /* not reached */ 932 933 case FFA_FEATURES: 934 /* 935 * This is an optional interface. Do the minimal checks and 936 * forward to SPM Core which will handle it if implemented. 937 */ 938 939 /* Forward SMC from Normal world to the SPM Core */ 940 if (!secure_origin) { 941 return spmd_smc_forward(smc_fid, secure_origin, 942 x1, x2, x3, x4, cookie, 943 handle, flags); 944 } 945 946 /* 947 * Return success if call was from secure world i.e. all 948 * FFA functions are supported. This is essentially a 949 * nop. 950 */ 951 SMC_RET8(handle, FFA_SUCCESS_SMC32, x1, x2, x3, x4, 952 SMC_GET_GP(handle, CTX_GPREG_X5), 953 SMC_GET_GP(handle, CTX_GPREG_X6), 954 SMC_GET_GP(handle, CTX_GPREG_X7)); 955 956 break; /* not reached */ 957 958 case FFA_ID_GET: 959 /* 960 * Returns the ID of the calling FFA component. 961 */ 962 if (!secure_origin) { 963 SMC_RET8(handle, FFA_SUCCESS_SMC32, 964 FFA_TARGET_INFO_MBZ, FFA_NS_ENDPOINT_ID, 965 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 966 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 967 FFA_PARAM_MBZ); 968 } 969 970 SMC_RET8(handle, FFA_SUCCESS_SMC32, 971 FFA_TARGET_INFO_MBZ, spmc_attrs.spmc_id, 972 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 973 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 974 FFA_PARAM_MBZ); 975 976 break; /* not reached */ 977 978 case FFA_SECONDARY_EP_REGISTER_SMC64: 979 if (secure_origin) { 980 ret = spmd_pm_secondary_ep_register(x1); 981 982 if (ret < 0) { 983 SMC_RET8(handle, FFA_ERROR_SMC64, 984 FFA_TARGET_INFO_MBZ, ret, 985 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 986 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 987 FFA_PARAM_MBZ); 988 } else { 989 SMC_RET8(handle, FFA_SUCCESS_SMC64, 990 FFA_TARGET_INFO_MBZ, FFA_PARAM_MBZ, 991 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 992 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 993 FFA_PARAM_MBZ); 994 } 995 } 996 997 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 998 break; /* Not reached */ 999 1000 case FFA_SPM_ID_GET: 1001 if (MAKE_FFA_VERSION(1, 1) > FFA_VERSION_COMPILED) { 1002 return spmd_ffa_error_return(handle, 1003 FFA_ERROR_NOT_SUPPORTED); 1004 } 1005 /* 1006 * Returns the ID of the SPMC or SPMD depending on the FF-A 1007 * instance where this function is invoked 1008 */ 1009 if (!secure_origin) { 1010 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1011 FFA_TARGET_INFO_MBZ, spmc_attrs.spmc_id, 1012 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1013 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1014 FFA_PARAM_MBZ); 1015 } 1016 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1017 FFA_TARGET_INFO_MBZ, SPMD_DIRECT_MSG_ENDPOINT_ID, 1018 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1019 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1020 FFA_PARAM_MBZ); 1021 1022 break; /* not reached */ 1023 1024 case FFA_MSG_SEND_DIRECT_REQ_SMC32: 1025 case FFA_MSG_SEND_DIRECT_REQ_SMC64: 1026 if (!secure_origin) { 1027 /* Validate source endpoint is non-secure for non-secure caller. */ 1028 if (ffa_is_secure_world_id(ffa_endpoint_source(x1))) { 1029 return spmd_ffa_error_return(handle, 1030 FFA_ERROR_INVALID_PARAMETER); 1031 } 1032 } 1033 if (secure_origin && spmd_is_spmc_message(x1)) { 1034 ret = spmd_handle_spmc_message(x3, x4, 1035 SMC_GET_GP(handle, CTX_GPREG_X5), 1036 SMC_GET_GP(handle, CTX_GPREG_X6), 1037 SMC_GET_GP(handle, CTX_GPREG_X7)); 1038 1039 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1040 FFA_TARGET_INFO_MBZ, ret, 1041 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1042 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1043 FFA_PARAM_MBZ); 1044 } else { 1045 /* Forward direct message to the other world */ 1046 return spmd_smc_forward(smc_fid, secure_origin, 1047 x1, x2, x3, x4, cookie, 1048 handle, flags); 1049 } 1050 break; /* Not reached */ 1051 1052 case FFA_MSG_SEND_DIRECT_RESP_SMC32: 1053 if (secure_origin && spmd_is_spmc_message(x1)) { 1054 spmd_spm_core_sync_exit(0ULL); 1055 } else { 1056 /* Forward direct message to the other world */ 1057 return spmd_smc_forward(smc_fid, secure_origin, 1058 x1, x2, x3, x4, cookie, 1059 handle, flags); 1060 } 1061 break; /* Not reached */ 1062 1063 case FFA_RX_RELEASE: 1064 case FFA_RXTX_MAP_SMC32: 1065 case FFA_RXTX_MAP_SMC64: 1066 case FFA_RXTX_UNMAP: 1067 case FFA_PARTITION_INFO_GET: 1068 #if MAKE_FFA_VERSION(1, 1) <= FFA_VERSION_COMPILED 1069 case FFA_NOTIFICATION_BITMAP_CREATE: 1070 case FFA_NOTIFICATION_BITMAP_DESTROY: 1071 case FFA_NOTIFICATION_BIND: 1072 case FFA_NOTIFICATION_UNBIND: 1073 case FFA_NOTIFICATION_SET: 1074 case FFA_NOTIFICATION_GET: 1075 case FFA_NOTIFICATION_INFO_GET: 1076 case FFA_NOTIFICATION_INFO_GET_SMC64: 1077 case FFA_MSG_SEND2: 1078 case FFA_RX_ACQUIRE: 1079 #endif 1080 case FFA_MSG_RUN: 1081 /* 1082 * Above calls should be invoked only by the Normal world and 1083 * must not be forwarded from Secure world to Normal world. 1084 */ 1085 if (secure_origin) { 1086 return spmd_ffa_error_return(handle, 1087 FFA_ERROR_NOT_SUPPORTED); 1088 } 1089 1090 /* Forward the call to the other world */ 1091 /* fallthrough */ 1092 case FFA_MSG_SEND: 1093 case FFA_MSG_SEND_DIRECT_RESP_SMC64: 1094 case FFA_MEM_DONATE_SMC32: 1095 case FFA_MEM_DONATE_SMC64: 1096 case FFA_MEM_LEND_SMC32: 1097 case FFA_MEM_LEND_SMC64: 1098 case FFA_MEM_SHARE_SMC32: 1099 case FFA_MEM_SHARE_SMC64: 1100 case FFA_MEM_RETRIEVE_REQ_SMC32: 1101 case FFA_MEM_RETRIEVE_REQ_SMC64: 1102 case FFA_MEM_RETRIEVE_RESP: 1103 case FFA_MEM_RELINQUISH: 1104 case FFA_MEM_RECLAIM: 1105 case FFA_MEM_FRAG_TX: 1106 case FFA_MEM_FRAG_RX: 1107 case FFA_SUCCESS_SMC32: 1108 case FFA_SUCCESS_SMC64: 1109 /* 1110 * TODO: Assume that no requests originate from EL3 at the 1111 * moment. This will change if a SP service is required in 1112 * response to secure interrupts targeted to EL3. Until then 1113 * simply forward the call to the Normal world. 1114 */ 1115 1116 return spmd_smc_forward(smc_fid, secure_origin, 1117 x1, x2, x3, x4, cookie, 1118 handle, flags); 1119 break; /* not reached */ 1120 1121 case FFA_MSG_WAIT: 1122 /* 1123 * Check if this is the first invocation of this interface on 1124 * this CPU from the Secure world. If so, then indicate that the 1125 * SPM Core initialised successfully. 1126 */ 1127 if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) { 1128 spmd_spm_core_sync_exit(0ULL); 1129 } 1130 1131 /* Forward the call to the other world */ 1132 /* fallthrough */ 1133 case FFA_INTERRUPT: 1134 case FFA_MSG_YIELD: 1135 /* This interface must be invoked only by the Secure world */ 1136 if (!secure_origin) { 1137 return spmd_ffa_error_return(handle, 1138 FFA_ERROR_NOT_SUPPORTED); 1139 } 1140 1141 return spmd_smc_forward(smc_fid, secure_origin, 1142 x1, x2, x3, x4, cookie, 1143 handle, flags); 1144 break; /* not reached */ 1145 1146 case FFA_NORMAL_WORLD_RESUME: 1147 if (secure_origin && ctx->secure_interrupt_ongoing) { 1148 spmd_spm_core_sync_exit(0ULL); 1149 } else { 1150 return spmd_ffa_error_return(handle, FFA_ERROR_DENIED); 1151 } 1152 break; /* Not reached */ 1153 #if MAKE_FFA_VERSION(1, 1) <= FFA_VERSION_COMPILED 1154 case FFA_PARTITION_INFO_GET_REGS_SMC64: 1155 if (secure_origin) { 1156 /* TODO: Future patches to enable support for this */ 1157 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1158 } 1159 1160 /* Call only supported with SMCCC 1.2+ */ 1161 if (MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION) < 0x10002) { 1162 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1163 } 1164 1165 return spmd_smc_forward(smc_fid, secure_origin, 1166 x1, x2, x3, x4, cookie, 1167 handle, flags); 1168 break; /* Not reached */ 1169 #endif 1170 case FFA_EL3_INTR_HANDLE: 1171 if (secure_origin) { 1172 return spmd_handle_group0_intr_swd(handle); 1173 } else { 1174 return spmd_ffa_error_return(handle, FFA_ERROR_DENIED); 1175 } 1176 default: 1177 WARN("SPM: Unsupported call 0x%08x\n", smc_fid); 1178 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1179 } 1180 } 1181