1 /* 2 * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/clk.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/stm32_gpio.h> 18 #include <drivers/st/stm32_sdmmc2.h> 19 #include <drivers/st/stm32mp_reset.h> 20 #include <lib/mmio.h> 21 #include <lib/utils.h> 22 #include <libfdt.h> 23 #include <plat/common/platform.h> 24 25 #include <platform_def.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_PWRCTRL_PWR_CYCLE BIT(1) 54 #define SDMMC_POWER_DIRPOL BIT(4) 55 56 /* SDMMC clock control register */ 57 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 58 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 59 #define SDMMC_CLKCR_NEGEDGE BIT(16) 60 #define SDMMC_CLKCR_HWFC_EN BIT(17) 61 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 62 63 /* SDMMC command register */ 64 #define SDMMC_CMDR_CMDTRANS BIT(6) 65 #define SDMMC_CMDR_CMDSTOP BIT(7) 66 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 67 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 68 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 69 #define SDMMC_CMDR_CPSMEN BIT(12) 70 71 /* SDMMC data control register */ 72 #define SDMMC_DCTRLR_DTEN BIT(0) 73 #define SDMMC_DCTRLR_DTDIR BIT(1) 74 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 75 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4 77 #define SDMMC_DCTRLR_FIFORST BIT(13) 78 79 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 80 SDMMC_DCTRLR_DTDIR | \ 81 SDMMC_DCTRLR_DTMODE | \ 82 SDMMC_DCTRLR_DBLOCKSIZE) 83 84 /* SDMMC status register */ 85 #define SDMMC_STAR_CCRCFAIL BIT(0) 86 #define SDMMC_STAR_DCRCFAIL BIT(1) 87 #define SDMMC_STAR_CTIMEOUT BIT(2) 88 #define SDMMC_STAR_DTIMEOUT BIT(3) 89 #define SDMMC_STAR_TXUNDERR BIT(4) 90 #define SDMMC_STAR_RXOVERR BIT(5) 91 #define SDMMC_STAR_CMDREND BIT(6) 92 #define SDMMC_STAR_CMDSENT BIT(7) 93 #define SDMMC_STAR_DATAEND BIT(8) 94 #define SDMMC_STAR_DBCKEND BIT(10) 95 #define SDMMC_STAR_DPSMACT BIT(12) 96 #define SDMMC_STAR_RXFIFOHF BIT(15) 97 #define SDMMC_STAR_RXFIFOE BIT(19) 98 #define SDMMC_STAR_IDMATE BIT(27) 99 #define SDMMC_STAR_IDMABTC BIT(28) 100 101 /* SDMMC DMA control register */ 102 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 103 104 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 105 SDMMC_STAR_DCRCFAIL | \ 106 SDMMC_STAR_CTIMEOUT | \ 107 SDMMC_STAR_DTIMEOUT | \ 108 SDMMC_STAR_TXUNDERR | \ 109 SDMMC_STAR_RXOVERR | \ 110 SDMMC_STAR_CMDREND | \ 111 SDMMC_STAR_CMDSENT | \ 112 SDMMC_STAR_DATAEND | \ 113 SDMMC_STAR_DBCKEND | \ 114 SDMMC_STAR_IDMATE | \ 115 SDMMC_STAR_IDMABTC) 116 117 #define TIMEOUT_US_1_MS 1000U 118 #define TIMEOUT_US_10_MS 10000U 119 #define TIMEOUT_US_1_S 1000000U 120 121 /* Power cycle delays in ms */ 122 #define VCC_POWER_OFF_DELAY 2 123 #define VCC_POWER_ON_DELAY 2 124 #define POWER_CYCLE_DELAY 2 125 #define POWER_OFF_DELAY 2 126 #define POWER_ON_DELAY 1 127 128 #ifndef DT_SDMMC2_COMPAT 129 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 130 #endif 131 132 #define SDMMC_FIFO_SIZE 64U 133 134 static void stm32_sdmmc2_init(void); 135 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 136 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 137 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 138 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 139 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 140 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 141 142 static const struct mmc_ops stm32_sdmmc2_ops = { 143 .init = stm32_sdmmc2_init, 144 .send_cmd = stm32_sdmmc2_send_cmd, 145 .set_ios = stm32_sdmmc2_set_ios, 146 .prepare = stm32_sdmmc2_prepare, 147 .read = stm32_sdmmc2_read, 148 .write = stm32_sdmmc2_write, 149 }; 150 151 static struct stm32_sdmmc2_params sdmmc2_params; 152 153 static bool next_cmd_is_acmd; 154 155 #pragma weak plat_sdmmc2_use_dma 156 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 157 { 158 return false; 159 } 160 161 static void stm32_sdmmc2_init(void) 162 { 163 uint32_t clock_div; 164 uint32_t freq = STM32MP_MMC_INIT_FREQ; 165 uintptr_t base = sdmmc2_params.reg_base; 166 int ret; 167 168 if (sdmmc2_params.max_freq != 0U) { 169 freq = MIN(sdmmc2_params.max_freq, freq); 170 } 171 172 if (sdmmc2_params.vmmc_regu != NULL) { 173 ret = regulator_disable(sdmmc2_params.vmmc_regu); 174 if (ret < 0) { 175 panic(); 176 } 177 } 178 179 mdelay(VCC_POWER_OFF_DELAY); 180 181 mmio_write_32(base + SDMMC_POWER, 182 SDMMC_POWER_PWRCTRL_PWR_CYCLE | sdmmc2_params.dirpol); 183 mdelay(POWER_CYCLE_DELAY); 184 185 if (sdmmc2_params.vmmc_regu != NULL) { 186 ret = regulator_enable(sdmmc2_params.vmmc_regu); 187 if (ret < 0) { 188 panic(); 189 } 190 } 191 192 mdelay(VCC_POWER_ON_DELAY); 193 194 mmio_write_32(base + SDMMC_POWER, sdmmc2_params.dirpol); 195 mdelay(POWER_OFF_DELAY); 196 197 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); 198 199 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 200 sdmmc2_params.negedge | 201 sdmmc2_params.pin_ckin); 202 203 mmio_write_32(base + SDMMC_POWER, 204 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 205 206 mdelay(POWER_ON_DELAY); 207 } 208 209 static int stm32_sdmmc2_stop_transfer(void) 210 { 211 struct mmc_cmd cmd_stop; 212 213 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 214 215 cmd_stop.cmd_idx = MMC_CMD(12); 216 cmd_stop.resp_type = MMC_RESPONSE_R1B; 217 218 return stm32_sdmmc2_send_cmd(&cmd_stop); 219 } 220 221 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 222 { 223 uint64_t timeout; 224 uint32_t flags_cmd, status; 225 uint32_t flags_data = 0; 226 int err = 0; 227 uintptr_t base = sdmmc2_params.reg_base; 228 unsigned int cmd_reg, arg_reg; 229 230 if (cmd == NULL) { 231 return -EINVAL; 232 } 233 234 flags_cmd = SDMMC_STAR_CTIMEOUT; 235 arg_reg = cmd->cmd_arg; 236 237 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 238 mmio_write_32(base + SDMMC_CMDR, 0); 239 } 240 241 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 242 243 if (cmd->resp_type == 0U) { 244 flags_cmd |= SDMMC_STAR_CMDSENT; 245 } 246 247 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 248 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 249 flags_cmd |= SDMMC_STAR_CMDREND; 250 cmd_reg |= SDMMC_CMDR_WAITRESP; 251 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 252 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 253 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 254 } else { 255 flags_cmd |= SDMMC_STAR_CMDREND; 256 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 257 } 258 } 259 260 switch (cmd->cmd_idx) { 261 case MMC_CMD(1): 262 arg_reg |= OCR_POWERUP; 263 break; 264 case MMC_CMD(6): 265 if ((sdmmc2_params.device_info->mmc_dev_type == MMC_IS_SD_HC) && 266 (!next_cmd_is_acmd)) { 267 cmd_reg |= SDMMC_CMDR_CMDTRANS; 268 if (sdmmc2_params.use_dma) { 269 flags_data |= SDMMC_STAR_DCRCFAIL | 270 SDMMC_STAR_DTIMEOUT | 271 SDMMC_STAR_DATAEND | 272 SDMMC_STAR_RXOVERR | 273 SDMMC_STAR_IDMATE | 274 SDMMC_STAR_DBCKEND; 275 } 276 } 277 break; 278 case MMC_CMD(8): 279 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 280 cmd_reg |= SDMMC_CMDR_CMDTRANS; 281 } 282 break; 283 case MMC_CMD(12): 284 cmd_reg |= SDMMC_CMDR_CMDSTOP; 285 break; 286 case MMC_CMD(17): 287 case MMC_CMD(18): 288 cmd_reg |= SDMMC_CMDR_CMDTRANS; 289 if (sdmmc2_params.use_dma) { 290 flags_data |= SDMMC_STAR_DCRCFAIL | 291 SDMMC_STAR_DTIMEOUT | 292 SDMMC_STAR_DATAEND | 293 SDMMC_STAR_RXOVERR | 294 SDMMC_STAR_IDMATE; 295 } 296 break; 297 case MMC_ACMD(41): 298 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 299 break; 300 case MMC_ACMD(51): 301 cmd_reg |= SDMMC_CMDR_CMDTRANS; 302 if (sdmmc2_params.use_dma) { 303 flags_data |= SDMMC_STAR_DCRCFAIL | 304 SDMMC_STAR_DTIMEOUT | 305 SDMMC_STAR_DATAEND | 306 SDMMC_STAR_RXOVERR | 307 SDMMC_STAR_IDMATE | 308 SDMMC_STAR_DBCKEND; 309 } 310 break; 311 default: 312 break; 313 } 314 315 next_cmd_is_acmd = (cmd->cmd_idx == MMC_CMD(55)); 316 317 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 318 319 /* 320 * Clear the SDMMC_DCTRLR if the command does not await data. 321 * Skip CMD55 as the next command could be data related, and 322 * the register could have been set in prepare function. 323 */ 324 if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) && !next_cmd_is_acmd) { 325 mmio_write_32(base + SDMMC_DCTRLR, 0U); 326 } 327 328 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 329 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 330 } 331 332 mmio_write_32(base + SDMMC_ARGR, arg_reg); 333 334 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 335 336 status = mmio_read_32(base + SDMMC_STAR); 337 338 timeout = timeout_init_us(TIMEOUT_US_10_MS); 339 340 while ((status & flags_cmd) == 0U) { 341 if (timeout_elapsed(timeout)) { 342 err = -ETIMEDOUT; 343 ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n", 344 __func__, cmd->cmd_idx, status); 345 goto err_exit; 346 } 347 348 status = mmio_read_32(base + SDMMC_STAR); 349 } 350 351 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) { 352 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 353 err = -ETIMEDOUT; 354 /* 355 * Those timeouts can occur, and framework will handle 356 * the retries. CMD8 is expected to return this timeout 357 * for eMMC 358 */ 359 if (!((cmd->cmd_idx == MMC_CMD(1)) || 360 (cmd->cmd_idx == MMC_CMD(13)) || 361 ((cmd->cmd_idx == MMC_CMD(8)) && 362 (cmd->resp_type == MMC_RESPONSE_R7)))) { 363 ERROR("%s: CTIMEOUT (cmd = %u,status = %x)\n", 364 __func__, cmd->cmd_idx, status); 365 } 366 } else { 367 err = -EIO; 368 ERROR("%s: CRCFAIL (cmd = %u,status = %x)\n", 369 __func__, cmd->cmd_idx, status); 370 } 371 372 goto err_exit; 373 } 374 375 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) { 376 if ((cmd->cmd_idx == MMC_CMD(9)) && 377 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 378 /* Need to invert response to match CSD structure */ 379 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 380 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 381 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 382 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 383 } else { 384 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 385 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 386 SDMMC_CMDR_WAITRESP) { 387 cmd->resp_data[1] = mmio_read_32(base + 388 SDMMC_RESP2R); 389 cmd->resp_data[2] = mmio_read_32(base + 390 SDMMC_RESP3R); 391 cmd->resp_data[3] = mmio_read_32(base + 392 SDMMC_RESP4R); 393 } 394 } 395 } 396 397 if (flags_data == 0U) { 398 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 399 400 return 0; 401 } 402 403 status = mmio_read_32(base + SDMMC_STAR); 404 405 timeout = timeout_init_us(TIMEOUT_US_10_MS); 406 407 while ((status & flags_data) == 0U) { 408 if (timeout_elapsed(timeout)) { 409 ERROR("%s: timeout 10ms (cmd = %u,status = %x)\n", 410 __func__, cmd->cmd_idx, status); 411 err = -ETIMEDOUT; 412 goto err_exit; 413 } 414 415 status = mmio_read_32(base + SDMMC_STAR); 416 }; 417 418 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 419 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 420 SDMMC_STAR_IDMATE)) != 0U) { 421 ERROR("%s: Error flag (cmd = %u,status = %x)\n", __func__, 422 cmd->cmd_idx, status); 423 err = -EIO; 424 } 425 426 err_exit: 427 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 428 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 429 430 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) { 431 int ret_stop = stm32_sdmmc2_stop_transfer(); 432 433 if (ret_stop != 0) { 434 return ret_stop; 435 } 436 } 437 438 return err; 439 } 440 441 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 442 { 443 uint8_t retry; 444 int err; 445 446 assert(cmd != NULL); 447 448 for (retry = 0U; retry < 3U; retry++) { 449 err = stm32_sdmmc2_send_cmd_req(cmd); 450 if (err == 0) { 451 return 0; 452 } 453 454 if ((cmd->cmd_idx == MMC_CMD(1)) || 455 (cmd->cmd_idx == MMC_CMD(13))) { 456 return 0; /* Retry managed by framework */ 457 } 458 459 /* Command 8 is expected to fail for eMMC */ 460 if (cmd->cmd_idx != MMC_CMD(8)) { 461 WARN(" CMD%u, Retry: %u, Error: %d\n", 462 cmd->cmd_idx, retry + 1U, err); 463 } 464 465 udelay(10U); 466 } 467 468 return err; 469 } 470 471 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 472 { 473 uintptr_t base = sdmmc2_params.reg_base; 474 uint32_t bus_cfg = 0; 475 uint32_t clock_div, max_freq, freq; 476 uint32_t clk_rate = sdmmc2_params.clk_rate; 477 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 478 479 switch (width) { 480 case MMC_BUS_WIDTH_1: 481 break; 482 case MMC_BUS_WIDTH_4: 483 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 484 break; 485 case MMC_BUS_WIDTH_8: 486 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 487 break; 488 default: 489 panic(); 490 break; 491 } 492 493 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 494 if (max_bus_freq >= 52000000U) { 495 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ; 496 } else { 497 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ; 498 } 499 } else { 500 if (max_bus_freq >= 50000000U) { 501 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ; 502 } else { 503 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ; 504 } 505 } 506 507 if (sdmmc2_params.max_freq != 0U) { 508 freq = MIN(sdmmc2_params.max_freq, max_freq); 509 } else { 510 freq = max_freq; 511 } 512 513 clock_div = div_round_up(clk_rate, freq * 2U); 514 515 mmio_write_32(base + SDMMC_CLKCR, 516 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 517 sdmmc2_params.negedge | 518 sdmmc2_params.pin_ckin); 519 520 return 0; 521 } 522 523 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 524 { 525 struct mmc_cmd cmd; 526 int ret; 527 uintptr_t base = sdmmc2_params.reg_base; 528 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 529 uint32_t arg_size; 530 531 assert(size != 0U); 532 533 if (size > MMC_BLOCK_SIZE) { 534 arg_size = MMC_BLOCK_SIZE; 535 } else { 536 arg_size = size; 537 } 538 539 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 540 541 if (sdmmc2_params.use_dma) { 542 inv_dcache_range(buf, size); 543 } 544 545 /* Prepare CMD 16*/ 546 mmio_write_32(base + SDMMC_DTIMER, 0); 547 548 mmio_write_32(base + SDMMC_DLENR, 0); 549 550 mmio_write_32(base + SDMMC_DCTRLR, 0); 551 552 zeromem(&cmd, sizeof(struct mmc_cmd)); 553 554 cmd.cmd_idx = MMC_CMD(16); 555 cmd.cmd_arg = arg_size; 556 cmd.resp_type = MMC_RESPONSE_R1; 557 558 ret = stm32_sdmmc2_send_cmd(&cmd); 559 if (ret != 0) { 560 ERROR("CMD16 failed\n"); 561 return ret; 562 } 563 564 /* Prepare data command */ 565 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 566 567 mmio_write_32(base + SDMMC_DLENR, size); 568 569 if (sdmmc2_params.use_dma) { 570 mmio_write_32(base + SDMMC_IDMACTRLR, 571 SDMMC_IDMACTRLR_IDMAEN); 572 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 573 574 flush_dcache_range(buf, size); 575 } 576 577 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT; 578 579 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 580 SDMMC_DCTRLR_CLEAR_MASK, 581 data_ctrl); 582 583 return 0; 584 } 585 586 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 587 { 588 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 589 SDMMC_STAR_DTIMEOUT; 590 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 591 uint32_t status; 592 uint32_t *buffer; 593 uintptr_t base = sdmmc2_params.reg_base; 594 uintptr_t fifo_reg = base + SDMMC_FIFOR; 595 uint64_t timeout; 596 int ret; 597 598 /* Assert buf is 4 bytes aligned */ 599 assert((buf & GENMASK(1, 0)) == 0U); 600 601 buffer = (uint32_t *)buf; 602 603 if (sdmmc2_params.use_dma) { 604 inv_dcache_range(buf, size); 605 606 return 0; 607 } 608 609 if (size <= MMC_BLOCK_SIZE) { 610 flags |= SDMMC_STAR_DBCKEND; 611 } 612 613 timeout = timeout_init_us(TIMEOUT_US_1_S); 614 615 do { 616 status = mmio_read_32(base + SDMMC_STAR); 617 618 if ((status & error_flags) != 0U) { 619 ERROR("%s: Read error (status = %x)\n", __func__, 620 status); 621 mmio_write_32(base + SDMMC_DCTRLR, 622 SDMMC_DCTRLR_FIFORST); 623 624 mmio_write_32(base + SDMMC_ICR, 625 SDMMC_STATIC_FLAGS); 626 627 ret = stm32_sdmmc2_stop_transfer(); 628 if (ret != 0) { 629 return ret; 630 } 631 632 return -EIO; 633 } 634 635 if (timeout_elapsed(timeout)) { 636 ERROR("%s: timeout 1s (status = %x)\n", 637 __func__, status); 638 mmio_write_32(base + SDMMC_ICR, 639 SDMMC_STATIC_FLAGS); 640 641 ret = stm32_sdmmc2_stop_transfer(); 642 if (ret != 0) { 643 return ret; 644 } 645 646 return -ETIMEDOUT; 647 } 648 649 if (size < (SDMMC_FIFO_SIZE / 2U)) { 650 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 651 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 652 *buffer = mmio_read_32(fifo_reg); 653 buffer++; 654 } 655 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 656 uint32_t count; 657 658 /* Read data from SDMMC Rx FIFO */ 659 for (count = 0; count < (SDMMC_FIFO_SIZE / 2U); 660 count += sizeof(uint32_t)) { 661 *buffer = mmio_read_32(fifo_reg); 662 buffer++; 663 } 664 } 665 } while ((status & flags) == 0U); 666 667 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 668 669 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 670 WARN("%s: DPSMACT=1, send stop\n", __func__); 671 return stm32_sdmmc2_stop_transfer(); 672 } 673 674 return 0; 675 } 676 677 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 678 { 679 return 0; 680 } 681 682 static int stm32_sdmmc2_dt_get_config(void) 683 { 684 int sdmmc_node; 685 void *fdt = NULL; 686 const fdt32_t *cuint; 687 struct dt_node_info dt_info; 688 689 if (fdt_get_address(&fdt) == 0) { 690 return -FDT_ERR_NOTFOUND; 691 } 692 693 if (fdt == NULL) { 694 return -FDT_ERR_NOTFOUND; 695 } 696 697 sdmmc_node = dt_match_instance_by_compatible(DT_SDMMC2_COMPAT, 698 sdmmc2_params.reg_base); 699 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 700 return -FDT_ERR_NOTFOUND; 701 } 702 703 dt_fill_device_info(&dt_info, sdmmc_node); 704 if (dt_info.status == DT_DISABLED) { 705 return -FDT_ERR_NOTFOUND; 706 } 707 708 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 709 return -FDT_ERR_BADVALUE; 710 } 711 712 sdmmc2_params.clock_id = dt_info.clock; 713 sdmmc2_params.reset_id = dt_info.reset; 714 715 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) { 716 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 717 } 718 719 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) { 720 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 721 } 722 723 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) { 724 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 725 } 726 727 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 728 if (cuint != NULL) { 729 switch (fdt32_to_cpu(*cuint)) { 730 case 4: 731 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 732 break; 733 734 case 8: 735 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 736 break; 737 738 default: 739 break; 740 } 741 } 742 743 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL); 744 if (cuint != NULL) { 745 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint); 746 } 747 748 sdmmc2_params.vmmc_regu = regulator_get_by_supply_name(fdt, sdmmc_node, "vmmc"); 749 750 return 0; 751 } 752 753 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 754 { 755 return sdmmc2_params.device_info->device_size; 756 } 757 758 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 759 { 760 assert((params != NULL) && 761 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 762 ((params->bus_width == MMC_BUS_WIDTH_1) || 763 (params->bus_width == MMC_BUS_WIDTH_4) || 764 (params->bus_width == MMC_BUS_WIDTH_8))); 765 766 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 767 768 sdmmc2_params.vmmc_regu = NULL; 769 770 if (stm32_sdmmc2_dt_get_config() != 0) { 771 ERROR("%s: DT error\n", __func__); 772 return -ENOMEM; 773 } 774 775 clk_enable(sdmmc2_params.clock_id); 776 777 if ((int)sdmmc2_params.reset_id >= 0) { 778 int rc; 779 780 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 781 if (rc != 0) { 782 panic(); 783 } 784 udelay(2); 785 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS); 786 if (rc != 0) { 787 panic(); 788 } 789 mdelay(1); 790 } 791 792 sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); 793 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4; 794 795 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 796 sdmmc2_params.bus_width, sdmmc2_params.flags, 797 sdmmc2_params.device_info); 798 } 799