xref: /rk3399_ARM-atf/plat/st/stm32mp1/stm32mp1_fip_def.h (revision e3a234971abb2402cbf376eca6fcb657a7709fae)
1 /*
2  * Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef STM32MP1_FIP_DEF_H
8 #define STM32MP1_FIP_DEF_H
9 
10 #define STM32MP_DDR_S_SIZE		U(0x01E00000)	/* 30 MB */
11 #define STM32MP_DDR_SHMEM_SIZE		U(0x00200000)	/* 2 MB */
12 
13 #define STM32MP_BL2_RO_SIZE		U(0x00011000)	/* 68 KB */
14 #define STM32MP_BL2_SIZE		U(0x00016000)	/* 88 KB for BL2 */
15 #define STM32MP_BL2_DTB_SIZE		U(0x00007000)	/* 28 KB for DTB */
16 #define STM32MP_BL32_SIZE		U(0x0001B000)	/* 108 KB for BL32 */
17 #define STM32MP_BL32_DTB_SIZE		U(0x00005000)	/* 20 KB for DTB */
18 #define STM32MP_FW_CONFIG_MAX_SIZE	PAGE_SIZE	/* 4 KB for FCONF DTB */
19 #define STM32MP_HW_CONFIG_MAX_SIZE	U(0x40000)	/* 256 KB for HW config DTB */
20 
21 #define STM32MP_BL2_BASE		(STM32MP_SEC_SYSRAM_BASE + \
22 					 STM32MP_SEC_SYSRAM_SIZE - \
23 					 STM32MP_BL2_SIZE)
24 
25 #define STM32MP_BL2_RO_BASE		STM32MP_BL2_BASE
26 
27 #define STM32MP_BL2_RW_BASE		(STM32MP_BL2_RO_BASE + \
28 					 STM32MP_BL2_RO_SIZE)
29 
30 #define STM32MP_BL2_RW_SIZE		(STM32MP_SEC_SYSRAM_BASE + \
31 					 STM32MP_SEC_SYSRAM_SIZE - \
32 					 STM32MP_BL2_RW_BASE)
33 
34 #define STM32MP_BL2_DTB_BASE		(STM32MP_BL2_BASE - \
35 					 STM32MP_BL2_DTB_SIZE)
36 
37 #define STM32MP_BL32_DTB_BASE		STM32MP_SYSRAM_BASE
38 
39 #define STM32MP_BL32_BASE		(STM32MP_BL32_DTB_BASE + \
40 					 STM32MP_BL32_DTB_SIZE)
41 
42 
43 #if defined(IMAGE_BL2)
44 #define STM32MP_DTB_SIZE		STM32MP_BL2_DTB_SIZE
45 #define STM32MP_DTB_BASE		STM32MP_BL2_DTB_BASE
46 #endif
47 #if defined(IMAGE_BL32)
48 #define STM32MP_DTB_SIZE		STM32MP_BL32_DTB_SIZE
49 #define STM32MP_DTB_BASE		STM32MP_BL32_DTB_BASE
50 #endif
51 
52 #ifdef AARCH32_SP_OPTEE
53 #define STM32MP_OPTEE_BASE		STM32MP_SEC_SYSRAM_BASE
54 
55 #define STM32MP_OPTEE_SIZE		(STM32MP_BL2_DTB_BASE -  \
56 					 STM32MP_OPTEE_BASE)
57 #endif
58 
59 #define STM32MP_FW_CONFIG_BASE		(STM32MP_SYSRAM_BASE + \
60 					 STM32MP_SYSRAM_SIZE - \
61 					 PAGE_SIZE)
62 #define STM32MP_HW_CONFIG_BASE		(STM32MP_BL33_BASE + \
63 					STM32MP_BL33_MAX_SIZE)
64 
65 /*
66  * MAX_MMAP_REGIONS is usually:
67  * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
68  */
69 #if defined(IMAGE_BL32)
70 #define MAX_MMAP_REGIONS		10
71 #endif
72 
73 /*******************************************************************************
74  * STM32MP1 RAW partition offset for MTD devices
75  ******************************************************************************/
76 #define STM32MP_NOR_FIP_OFFSET		U(0x00080000)
77 #define STM32MP_NAND_FIP_OFFSET		U(0x00200000)
78 
79 #endif /* STM32MP1_FIP_DEF_H */
80