1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/clk.h> 10 #include <drivers/st/stm32_gpio.h> 11 #include <drivers/st/stm32_iwdg.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <libfdt.h> 15 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 #if STM32MP13 20 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(30) 21 #endif 22 #if STM32MP15 23 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) 24 #endif 25 26 /* 27 * Backup register to store fwu update information. 28 * It should be writeable only by secure world, but also readable by non secure 29 * (so it should be in Zone 2). 30 */ 31 #define TAMP_BOOT_FWU_INFO_REG_ID U(10) 32 33 #if defined(IMAGE_BL2) 34 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 35 STM32MP_SYSRAM_SIZE, \ 36 MT_MEMORY | \ 37 MT_RW | \ 38 MT_SECURE | \ 39 MT_EXECUTE_NEVER) 40 #elif defined(IMAGE_BL32) 41 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 42 STM32MP_SEC_SYSRAM_SIZE, \ 43 MT_MEMORY | \ 44 MT_RW | \ 45 MT_SECURE | \ 46 MT_EXECUTE_NEVER) 47 48 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 49 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 50 STM32MP_NS_SYSRAM_SIZE, \ 51 MT_DEVICE | \ 52 MT_RW | \ 53 MT_NS | \ 54 MT_EXECUTE_NEVER) 55 #endif 56 57 #if STM32MP13 58 #define MAP_SRAM_ALL MAP_REGION_FLAT(SRAMS_BASE, \ 59 SRAMS_SIZE_2MB_ALIGNED, \ 60 MT_MEMORY | \ 61 MT_RW | \ 62 MT_SECURE | \ 63 MT_EXECUTE_NEVER) 64 #endif 65 66 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 67 STM32MP1_DEVICE1_SIZE, \ 68 MT_DEVICE | \ 69 MT_RW | \ 70 MT_SECURE | \ 71 MT_EXECUTE_NEVER) 72 73 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 74 STM32MP1_DEVICE2_SIZE, \ 75 MT_DEVICE | \ 76 MT_RW | \ 77 MT_SECURE | \ 78 MT_EXECUTE_NEVER) 79 80 #if defined(IMAGE_BL2) 81 static const mmap_region_t stm32mp1_mmap[] = { 82 MAP_SEC_SYSRAM, 83 #if STM32MP13 84 MAP_SRAM_ALL, 85 #endif 86 MAP_DEVICE1, 87 #if STM32MP_RAW_NAND 88 MAP_DEVICE2, 89 #endif 90 {0} 91 }; 92 #endif 93 #if defined(IMAGE_BL32) 94 static const mmap_region_t stm32mp1_mmap[] = { 95 MAP_SEC_SYSRAM, 96 MAP_NS_SYSRAM, 97 MAP_DEVICE1, 98 MAP_DEVICE2, 99 {0} 100 }; 101 #endif 102 103 void configure_mmu(void) 104 { 105 mmap_add(stm32mp1_mmap); 106 init_xlat_tables(); 107 108 enable_mmu_svc_mon(0); 109 } 110 111 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 112 { 113 #if STM32MP13 114 assert(bank <= GPIO_BANK_I); 115 #endif 116 #if STM32MP15 117 if (bank == GPIO_BANK_Z) { 118 return GPIOZ_BASE; 119 } 120 121 assert(bank <= GPIO_BANK_K); 122 #endif 123 124 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 125 } 126 127 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 128 { 129 #if STM32MP13 130 assert(bank <= GPIO_BANK_I); 131 #endif 132 #if STM32MP15 133 if (bank == GPIO_BANK_Z) { 134 return 0; 135 } 136 137 assert(bank <= GPIO_BANK_K); 138 #endif 139 140 return bank * GPIO_BANK_OFFSET; 141 } 142 143 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 144 { 145 #if STM32MP13 146 return true; 147 #endif 148 #if STM32MP15 149 if (bank == GPIO_BANK_Z) { 150 return true; 151 } 152 153 return false; 154 #endif 155 } 156 157 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 158 { 159 #if STM32MP13 160 assert(bank <= GPIO_BANK_I); 161 #endif 162 #if STM32MP15 163 if (bank == GPIO_BANK_Z) { 164 return GPIOZ; 165 } 166 167 assert(bank <= GPIO_BANK_K); 168 #endif 169 170 return GPIOA + (bank - GPIO_BANK_A); 171 } 172 173 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 174 { 175 const char *node_compatible = NULL; 176 177 switch (bank) { 178 case GPIO_BANK_A: 179 case GPIO_BANK_B: 180 case GPIO_BANK_C: 181 case GPIO_BANK_D: 182 case GPIO_BANK_E: 183 case GPIO_BANK_F: 184 case GPIO_BANK_G: 185 case GPIO_BANK_H: 186 case GPIO_BANK_I: 187 #if STM32MP13 188 node_compatible = "st,stm32mp135-pinctrl"; 189 break; 190 #endif 191 #if STM32MP15 192 case GPIO_BANK_J: 193 case GPIO_BANK_K: 194 node_compatible = "st,stm32mp157-pinctrl"; 195 break; 196 case GPIO_BANK_Z: 197 node_compatible = "st,stm32mp157-z-pinctrl"; 198 break; 199 #endif 200 default: 201 panic(); 202 } 203 204 return fdt_node_offset_by_compatible(fdt, -1, node_compatible); 205 } 206 207 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 208 /* 209 * UART Management 210 */ 211 static const uintptr_t stm32mp1_uart_addresses[8] = { 212 USART1_BASE, 213 USART2_BASE, 214 USART3_BASE, 215 UART4_BASE, 216 UART5_BASE, 217 USART6_BASE, 218 UART7_BASE, 219 UART8_BASE, 220 }; 221 222 uintptr_t get_uart_address(uint32_t instance_nb) 223 { 224 if ((instance_nb == 0U) || 225 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 226 return 0U; 227 } 228 229 return stm32mp1_uart_addresses[instance_nb - 1U]; 230 } 231 #endif 232 233 #if STM32MP_USB_PROGRAMMER 234 struct gpio_bank_pin_list { 235 uint32_t bank; 236 uint32_t pin; 237 }; 238 239 static const struct gpio_bank_pin_list gpio_list[] = { 240 { /* USART2_RX: GPIOA3 */ 241 .bank = 0U, 242 .pin = 3U, 243 }, 244 { /* USART3_RX: GPIOB12 */ 245 .bank = 1U, 246 .pin = 12U, 247 }, 248 { /* UART4_RX: GPIOB2 */ 249 .bank = 1U, 250 .pin = 2U, 251 }, 252 { /* UART5_RX: GPIOB4 */ 253 .bank = 1U, 254 .pin = 5U, 255 }, 256 { /* USART6_RX: GPIOC7 */ 257 .bank = 2U, 258 .pin = 7U, 259 }, 260 { /* UART7_RX: GPIOF6 */ 261 .bank = 5U, 262 .pin = 6U, 263 }, 264 { /* UART8_RX: GPIOE0 */ 265 .bank = 4U, 266 .pin = 0U, 267 }, 268 }; 269 270 void stm32mp1_deconfigure_uart_pins(void) 271 { 272 size_t i; 273 274 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) { 275 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin); 276 } 277 } 278 #endif 279 280 uint32_t stm32mp_get_chip_version(void) 281 { 282 #if STM32MP13 283 return stm32mp_syscfg_get_chip_version(); 284 #endif 285 #if STM32MP15 286 uint32_t version = 0U; 287 288 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 289 INFO("Cannot get CPU version, debug disabled\n"); 290 return 0U; 291 } 292 293 return version; 294 #endif 295 } 296 297 uint32_t stm32mp_get_chip_dev_id(void) 298 { 299 #if STM32MP13 300 return stm32mp_syscfg_get_chip_dev_id(); 301 #endif 302 #if STM32MP15 303 uint32_t dev_id; 304 305 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 306 INFO("Use default chip ID, debug disabled\n"); 307 dev_id = STM32MP1_CHIP_ID; 308 } 309 310 return dev_id; 311 #endif 312 } 313 314 static uint32_t get_part_number(void) 315 { 316 static uint32_t part_number; 317 318 if (part_number != 0U) { 319 return part_number; 320 } 321 322 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 323 panic(); 324 } 325 326 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 327 PART_NUMBER_OTP_PART_SHIFT; 328 329 part_number |= stm32mp_get_chip_dev_id() << 16; 330 331 return part_number; 332 } 333 334 #if STM32MP15 335 static uint32_t get_cpu_package(void) 336 { 337 uint32_t package; 338 339 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 340 panic(); 341 } 342 343 package = (package & PACKAGE_OTP_PKG_MASK) >> 344 PACKAGE_OTP_PKG_SHIFT; 345 346 return package; 347 } 348 #endif 349 350 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 351 { 352 const char *cpu_s, *cpu_r, *pkg; 353 354 /* MPUs Part Numbers */ 355 switch (get_part_number()) { 356 #if STM32MP13 357 case STM32MP135F_PART_NB: 358 cpu_s = "135F"; 359 break; 360 case STM32MP135D_PART_NB: 361 cpu_s = "135D"; 362 break; 363 case STM32MP135C_PART_NB: 364 cpu_s = "135C"; 365 break; 366 case STM32MP135A_PART_NB: 367 cpu_s = "135A"; 368 break; 369 case STM32MP133F_PART_NB: 370 cpu_s = "133F"; 371 break; 372 case STM32MP133D_PART_NB: 373 cpu_s = "133D"; 374 break; 375 case STM32MP133C_PART_NB: 376 cpu_s = "133C"; 377 break; 378 case STM32MP133A_PART_NB: 379 cpu_s = "133A"; 380 break; 381 case STM32MP131F_PART_NB: 382 cpu_s = "131F"; 383 break; 384 case STM32MP131D_PART_NB: 385 cpu_s = "131D"; 386 break; 387 case STM32MP131C_PART_NB: 388 cpu_s = "131C"; 389 break; 390 case STM32MP131A_PART_NB: 391 cpu_s = "131A"; 392 break; 393 #endif 394 #if STM32MP15 395 case STM32MP157C_PART_NB: 396 cpu_s = "157C"; 397 break; 398 case STM32MP157A_PART_NB: 399 cpu_s = "157A"; 400 break; 401 case STM32MP153C_PART_NB: 402 cpu_s = "153C"; 403 break; 404 case STM32MP153A_PART_NB: 405 cpu_s = "153A"; 406 break; 407 case STM32MP151C_PART_NB: 408 cpu_s = "151C"; 409 break; 410 case STM32MP151A_PART_NB: 411 cpu_s = "151A"; 412 break; 413 case STM32MP157F_PART_NB: 414 cpu_s = "157F"; 415 break; 416 case STM32MP157D_PART_NB: 417 cpu_s = "157D"; 418 break; 419 case STM32MP153F_PART_NB: 420 cpu_s = "153F"; 421 break; 422 case STM32MP153D_PART_NB: 423 cpu_s = "153D"; 424 break; 425 case STM32MP151F_PART_NB: 426 cpu_s = "151F"; 427 break; 428 case STM32MP151D_PART_NB: 429 cpu_s = "151D"; 430 break; 431 #endif 432 default: 433 cpu_s = "????"; 434 break; 435 } 436 437 /* Package */ 438 #if STM32MP13 439 /* On STM32MP13, package is not present in OTP */ 440 pkg = ""; 441 #endif 442 #if STM32MP15 443 switch (get_cpu_package()) { 444 case PKG_AA_LFBGA448: 445 pkg = "AA"; 446 break; 447 case PKG_AB_LFBGA354: 448 pkg = "AB"; 449 break; 450 case PKG_AC_TFBGA361: 451 pkg = "AC"; 452 break; 453 case PKG_AD_TFBGA257: 454 pkg = "AD"; 455 break; 456 default: 457 pkg = "??"; 458 break; 459 } 460 #endif 461 462 /* REVISION */ 463 switch (stm32mp_get_chip_version()) { 464 case STM32MP1_REV_B: 465 cpu_r = "B"; 466 break; 467 #if STM32MP13 468 case STM32MP1_REV_Y: 469 cpu_r = "Y"; 470 break; 471 #endif 472 case STM32MP1_REV_Z: 473 cpu_r = "Z"; 474 break; 475 default: 476 cpu_r = "?"; 477 break; 478 } 479 480 snprintf(name, STM32_SOC_NAME_SIZE, 481 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 482 } 483 484 void stm32mp_print_cpuinfo(void) 485 { 486 char name[STM32_SOC_NAME_SIZE]; 487 488 stm32mp_get_soc_name(name); 489 NOTICE("CPU: %s\n", name); 490 } 491 492 void stm32mp_print_boardinfo(void) 493 { 494 uint32_t board_id = 0U; 495 496 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 497 return; 498 } 499 500 if (board_id != 0U) { 501 stm32_display_board_info(board_id); 502 } 503 } 504 505 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 506 bool stm32mp_is_single_core(void) 507 { 508 #if STM32MP13 509 return true; 510 #endif 511 #if STM32MP15 512 bool single_core = false; 513 514 switch (get_part_number()) { 515 case STM32MP151A_PART_NB: 516 case STM32MP151C_PART_NB: 517 case STM32MP151D_PART_NB: 518 case STM32MP151F_PART_NB: 519 single_core = true; 520 break; 521 default: 522 break; 523 } 524 525 return single_core; 526 #endif 527 } 528 529 /* Return true when device is in closed state */ 530 uint32_t stm32mp_check_closed_device(void) 531 { 532 uint32_t value; 533 534 if (stm32_get_otp_value(CFG0_OTP, &value) != 0) { 535 return STM32MP_CHIP_SEC_CLOSED; 536 } 537 538 #if STM32MP13 539 value = (value & CFG0_OTP_MODE_MASK) >> CFG0_OTP_MODE_SHIFT; 540 541 switch (value) { 542 case CFG0_OPEN_DEVICE: 543 return STM32MP_CHIP_SEC_OPEN; 544 case CFG0_CLOSED_DEVICE: 545 case CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN: 546 case CFG0_CLOSED_DEVICE_NO_JTAG: 547 return STM32MP_CHIP_SEC_CLOSED; 548 default: 549 panic(); 550 } 551 #endif 552 #if STM32MP15 553 if ((value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE) { 554 return STM32MP_CHIP_SEC_CLOSED; 555 } else { 556 return STM32MP_CHIP_SEC_OPEN; 557 } 558 559 #endif 560 } 561 562 /* Return true when device supports secure boot */ 563 bool stm32mp_is_auth_supported(void) 564 { 565 bool supported = false; 566 567 switch (get_part_number()) { 568 #if STM32MP13 569 case STM32MP131C_PART_NB: 570 case STM32MP131F_PART_NB: 571 case STM32MP133C_PART_NB: 572 case STM32MP133F_PART_NB: 573 case STM32MP135C_PART_NB: 574 case STM32MP135F_PART_NB: 575 #endif 576 #if STM32MP15 577 case STM32MP151C_PART_NB: 578 case STM32MP151F_PART_NB: 579 case STM32MP153C_PART_NB: 580 case STM32MP153F_PART_NB: 581 case STM32MP157C_PART_NB: 582 case STM32MP157F_PART_NB: 583 #endif 584 supported = true; 585 break; 586 default: 587 break; 588 } 589 590 return supported; 591 } 592 593 uint32_t stm32_iwdg_get_instance(uintptr_t base) 594 { 595 switch (base) { 596 case IWDG1_BASE: 597 return IWDG1_INST; 598 case IWDG2_BASE: 599 return IWDG2_INST; 600 default: 601 panic(); 602 } 603 } 604 605 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 606 { 607 uint32_t iwdg_cfg = 0U; 608 uint32_t otp_value; 609 610 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 611 panic(); 612 } 613 614 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 615 iwdg_cfg |= IWDG_HW_ENABLED; 616 } 617 618 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 619 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 620 } 621 622 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 623 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 624 } 625 626 return iwdg_cfg; 627 } 628 629 #if defined(IMAGE_BL2) 630 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 631 { 632 uint32_t otp_value; 633 uint32_t otp; 634 uint32_t result; 635 636 if (stm32_get_otp_index(HW2_OTP, &otp, NULL) != 0) { 637 panic(); 638 } 639 640 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 641 panic(); 642 } 643 644 if ((flags & IWDG_DISABLE_ON_STOP) != 0) { 645 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 646 } 647 648 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0) { 649 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 650 } 651 652 result = bsec_write_otp(otp_value, otp); 653 if (result != BSEC_OK) { 654 return result; 655 } 656 657 /* Sticky lock OTP_IWDG (read and write) */ 658 if ((bsec_set_sr_lock(otp) != BSEC_OK) || 659 (bsec_set_sw_lock(otp) != BSEC_OK)) { 660 return BSEC_LOCK_FAIL; 661 } 662 663 return BSEC_OK; 664 } 665 #endif 666 667 bool stm32mp_is_wakeup_from_standby(void) 668 { 669 /* TODO add source code to determine if platform is waking up from standby mode */ 670 return false; 671 } 672 673 uintptr_t stm32_get_bkpr_boot_mode_addr(void) 674 { 675 return tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 676 } 677 678 #if PSA_FWU_SUPPORT 679 uintptr_t stm32_get_bkpr_fwu_info_addr(void) 680 { 681 return tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID); 682 } 683 #endif /* PSA_FWU_SUPPORT */ 684