1 /* 2 * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <inttypes.h> 8 #include <libfdt.h> 9 10 #include <platform_def.h> 11 12 #include <common/debug.h> 13 #include <common/fdt_wrappers.h> 14 #include <drivers/clk.h> 15 #include <drivers/delay_timer.h> 16 #include <drivers/spi_mem.h> 17 #include <drivers/st/stm32_gpio.h> 18 #include <drivers/st/stm32_qspi.h> 19 #include <drivers/st/stm32mp_reset.h> 20 #include <lib/mmio.h> 21 #include <lib/utils_def.h> 22 23 /* Timeout for device interface reset */ 24 #define TIMEOUT_US_1_MS 1000U 25 26 /* QUADSPI registers */ 27 #define QSPI_CR 0x00U 28 #define QSPI_DCR 0x04U 29 #define QSPI_SR 0x08U 30 #define QSPI_FCR 0x0CU 31 #define QSPI_DLR 0x10U 32 #define QSPI_CCR 0x14U 33 #define QSPI_AR 0x18U 34 #define QSPI_ABR 0x1CU 35 #define QSPI_DR 0x20U 36 #define QSPI_PSMKR 0x24U 37 #define QSPI_PSMAR 0x28U 38 #define QSPI_PIR 0x2CU 39 #define QSPI_LPTR 0x30U 40 41 /* QUADSPI control register */ 42 #define QSPI_CR_EN BIT(0) 43 #define QSPI_CR_ABORT BIT(1) 44 #define QSPI_CR_DMAEN BIT(2) 45 #define QSPI_CR_TCEN BIT(3) 46 #define QSPI_CR_SSHIFT BIT(4) 47 #define QSPI_CR_DFM BIT(6) 48 #define QSPI_CR_FSEL BIT(7) 49 #define QSPI_CR_FTHRES_SHIFT 8U 50 #define QSPI_CR_TEIE BIT(16) 51 #define QSPI_CR_TCIE BIT(17) 52 #define QSPI_CR_FTIE BIT(18) 53 #define QSPI_CR_SMIE BIT(19) 54 #define QSPI_CR_TOIE BIT(20) 55 #define QSPI_CR_APMS BIT(22) 56 #define QSPI_CR_PMM BIT(23) 57 #define QSPI_CR_PRESCALER_MASK GENMASK_32(31, 24) 58 #define QSPI_CR_PRESCALER_SHIFT 24U 59 60 /* QUADSPI device configuration register */ 61 #define QSPI_DCR_CKMODE BIT(0) 62 #define QSPI_DCR_CSHT_MASK GENMASK_32(10, 8) 63 #define QSPI_DCR_CSHT_SHIFT 8U 64 #define QSPI_DCR_FSIZE_MASK GENMASK_32(20, 16) 65 #define QSPI_DCR_FSIZE_SHIFT 16U 66 67 /* QUADSPI status register */ 68 #define QSPI_SR_TEF BIT(0) 69 #define QSPI_SR_TCF BIT(1) 70 #define QSPI_SR_FTF BIT(2) 71 #define QSPI_SR_SMF BIT(3) 72 #define QSPI_SR_TOF BIT(4) 73 #define QSPI_SR_BUSY BIT(5) 74 75 /* QUADSPI flag clear register */ 76 #define QSPI_FCR_CTEF BIT(0) 77 #define QSPI_FCR_CTCF BIT(1) 78 #define QSPI_FCR_CSMF BIT(3) 79 #define QSPI_FCR_CTOF BIT(4) 80 81 /* QUADSPI communication configuration register */ 82 #define QSPI_CCR_DDRM BIT(31) 83 #define QSPI_CCR_DHHC BIT(30) 84 #define QSPI_CCR_SIOO BIT(28) 85 #define QSPI_CCR_FMODE_SHIFT 26U 86 #define QSPI_CCR_DMODE_SHIFT 24U 87 #define QSPI_CCR_DCYC_SHIFT 18U 88 #define QSPI_CCR_ABSIZE_SHIFT 16U 89 #define QSPI_CCR_ABMODE_SHIFT 14U 90 #define QSPI_CCR_ADSIZE_SHIFT 12U 91 #define QSPI_CCR_ADMODE_SHIFT 10U 92 #define QSPI_CCR_IMODE_SHIFT 8U 93 #define QSPI_CCR_IND_WRITE 0U 94 #define QSPI_CCR_IND_READ 1U 95 #define QSPI_CCR_MEM_MAP 3U 96 97 #define QSPI_MAX_CHIP 2U 98 99 #define QSPI_FIFO_TIMEOUT_US 30U 100 #define QSPI_CMD_TIMEOUT_US 1000U 101 #define QSPI_BUSY_TIMEOUT_US 100U 102 #define QSPI_ABT_TIMEOUT_US 100U 103 104 #define DT_QSPI_COMPAT "st,stm32f469-qspi" 105 106 #define FREQ_100MHZ 100000000U 107 108 struct stm32_qspi_ctrl { 109 uintptr_t reg_base; 110 uintptr_t mm_base; 111 size_t mm_size; 112 unsigned long clock_id; 113 unsigned int reset_id; 114 }; 115 116 static struct stm32_qspi_ctrl stm32_qspi; 117 118 static uintptr_t qspi_base(void) 119 { 120 return stm32_qspi.reg_base; 121 } 122 123 static int stm32_qspi_wait_for_not_busy(void) 124 { 125 uint64_t timeout = timeout_init_us(QSPI_BUSY_TIMEOUT_US); 126 127 while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_BUSY) != 0U) { 128 if (timeout_elapsed(timeout)) { 129 ERROR("%s: busy timeout\n", __func__); 130 return -ETIMEDOUT; 131 } 132 } 133 134 return 0; 135 } 136 137 static int stm32_qspi_wait_cmd(const struct spi_mem_op *op) 138 { 139 int ret = 0; 140 uint64_t timeout; 141 142 if (op->data.nbytes == 0U) { 143 return stm32_qspi_wait_for_not_busy(); 144 } 145 146 timeout = timeout_init_us(QSPI_CMD_TIMEOUT_US); 147 while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TCF) == 0U) { 148 if (timeout_elapsed(timeout)) { 149 ret = -ETIMEDOUT; 150 break; 151 } 152 } 153 154 if (ret == 0) { 155 if ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TEF) != 0U) { 156 ERROR("%s: transfer error\n", __func__); 157 ret = -EIO; 158 } 159 } else { 160 ERROR("%s: cmd timeout\n", __func__); 161 } 162 163 /* Clear flags */ 164 mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF | QSPI_FCR_CTEF); 165 166 return ret; 167 } 168 169 static void stm32_qspi_read_fifo(uint8_t *val, uintptr_t addr) 170 { 171 *val = mmio_read_8(addr); 172 } 173 174 static void stm32_qspi_write_fifo(uint8_t *val, uintptr_t addr) 175 { 176 mmio_write_8(addr, *val); 177 } 178 179 static int stm32_qspi_poll(const struct spi_mem_op *op) 180 { 181 void (*fifo)(uint8_t *val, uintptr_t addr); 182 uint32_t len; 183 uint8_t *buf; 184 185 if (op->data.dir == SPI_MEM_DATA_IN) { 186 fifo = stm32_qspi_read_fifo; 187 } else { 188 fifo = stm32_qspi_write_fifo; 189 } 190 191 buf = (uint8_t *)op->data.buf; 192 193 for (len = op->data.nbytes; len != 0U; len--) { 194 uint64_t timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US); 195 196 while ((mmio_read_32(qspi_base() + QSPI_SR) & 197 QSPI_SR_FTF) == 0U) { 198 if (timeout_elapsed(timeout)) { 199 ERROR("%s: fifo timeout\n", __func__); 200 return -ETIMEDOUT; 201 } 202 } 203 204 fifo(buf++, qspi_base() + QSPI_DR); 205 } 206 207 return 0; 208 } 209 210 static int stm32_qspi_mm(const struct spi_mem_op *op) 211 { 212 memcpy(op->data.buf, 213 (void *)(stm32_qspi.mm_base + (size_t)op->addr.val), 214 op->data.nbytes); 215 216 return 0; 217 } 218 219 static int stm32_qspi_tx(const struct spi_mem_op *op, uint8_t mode) 220 { 221 if (op->data.nbytes == 0U) { 222 return 0; 223 } 224 225 if (mode == QSPI_CCR_MEM_MAP) { 226 return stm32_qspi_mm(op); 227 } 228 229 return stm32_qspi_poll(op); 230 } 231 232 static unsigned int stm32_qspi_get_mode(uint8_t buswidth) 233 { 234 if (buswidth == 4U) { 235 return 3U; 236 } 237 238 return buswidth; 239 } 240 241 static int stm32_qspi_exec_op(const struct spi_mem_op *op) 242 { 243 uint64_t timeout; 244 uint32_t ccr; 245 size_t addr_max; 246 uint8_t mode = QSPI_CCR_IND_WRITE; 247 int ret; 248 249 VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addr:%" PRIx64 " len:%x\n", 250 __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 251 op->dummy.buswidth, op->data.buswidth, 252 op->addr.val, op->data.nbytes); 253 254 ret = stm32_qspi_wait_for_not_busy(); 255 if (ret != 0) { 256 return ret; 257 } 258 259 addr_max = op->addr.val + op->data.nbytes + 1U; 260 261 if ((op->data.dir == SPI_MEM_DATA_IN) && (op->data.nbytes != 0U)) { 262 if ((addr_max < stm32_qspi.mm_size) && 263 (op->addr.buswidth != 0U)) { 264 mode = QSPI_CCR_MEM_MAP; 265 } else { 266 mode = QSPI_CCR_IND_READ; 267 } 268 } 269 270 if (op->data.nbytes != 0U) { 271 mmio_write_32(qspi_base() + QSPI_DLR, op->data.nbytes - 1U); 272 } 273 274 ccr = mode << QSPI_CCR_FMODE_SHIFT; 275 ccr |= op->cmd.opcode; 276 ccr |= stm32_qspi_get_mode(op->cmd.buswidth) << QSPI_CCR_IMODE_SHIFT; 277 278 if (op->addr.nbytes != 0U) { 279 ccr |= (op->addr.nbytes - 1U) << QSPI_CCR_ADSIZE_SHIFT; 280 ccr |= stm32_qspi_get_mode(op->addr.buswidth) << 281 QSPI_CCR_ADMODE_SHIFT; 282 } 283 284 if ((op->dummy.buswidth != 0U) && (op->dummy.nbytes != 0U)) { 285 ccr |= (op->dummy.nbytes * 8U / op->dummy.buswidth) << 286 QSPI_CCR_DCYC_SHIFT; 287 } 288 289 if (op->data.nbytes != 0U) { 290 ccr |= stm32_qspi_get_mode(op->data.buswidth) << 291 QSPI_CCR_DMODE_SHIFT; 292 } 293 294 mmio_write_32(qspi_base() + QSPI_CCR, ccr); 295 296 if ((op->addr.nbytes != 0U) && (mode != QSPI_CCR_MEM_MAP)) { 297 mmio_write_32(qspi_base() + QSPI_AR, op->addr.val); 298 } 299 300 ret = stm32_qspi_tx(op, mode); 301 302 /* 303 * Abort in: 304 * - Error case. 305 * - Memory mapped read: prefetching must be stopped if we read the last 306 * byte of device (device size - fifo size). If device size is not 307 * known then prefetching is always stopped. 308 */ 309 if ((ret != 0) || (mode == QSPI_CCR_MEM_MAP)) { 310 goto abort; 311 } 312 313 /* Wait end of TX in indirect mode */ 314 ret = stm32_qspi_wait_cmd(op); 315 if (ret != 0) { 316 goto abort; 317 } 318 319 return 0; 320 321 abort: 322 mmio_setbits_32(qspi_base() + QSPI_CR, QSPI_CR_ABORT); 323 324 /* Wait clear of abort bit by hardware */ 325 timeout = timeout_init_us(QSPI_ABT_TIMEOUT_US); 326 while ((mmio_read_32(qspi_base() + QSPI_CR) & QSPI_CR_ABORT) != 0U) { 327 if (timeout_elapsed(timeout)) { 328 ret = -ETIMEDOUT; 329 break; 330 } 331 } 332 333 mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF); 334 335 if (ret != 0) { 336 ERROR("%s: exec op error\n", __func__); 337 } 338 339 return ret; 340 } 341 342 static int stm32_qspi_claim_bus(unsigned int cs) 343 { 344 uint32_t cr; 345 346 if (cs >= QSPI_MAX_CHIP) { 347 return -ENODEV; 348 } 349 350 /* Set chip select and enable the controller */ 351 cr = QSPI_CR_EN; 352 if (cs == 1U) { 353 cr |= QSPI_CR_FSEL; 354 } 355 356 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_FSEL, cr); 357 358 return 0; 359 } 360 361 static void stm32_qspi_release_bus(void) 362 { 363 mmio_clrbits_32(qspi_base() + QSPI_CR, QSPI_CR_EN); 364 } 365 366 static int stm32_qspi_set_speed(unsigned int hz) 367 { 368 unsigned long qspi_clk = clk_get_rate(stm32_qspi.clock_id); 369 uint32_t prescaler = UINT8_MAX; 370 uint32_t csht; 371 int ret; 372 373 if (qspi_clk == 0U) { 374 return -EINVAL; 375 } 376 377 if (hz > 0U) { 378 prescaler = div_round_up(qspi_clk, hz) - 1U; 379 if (prescaler > UINT8_MAX) { 380 prescaler = UINT8_MAX; 381 } 382 } 383 384 csht = div_round_up((5U * qspi_clk) / (prescaler + 1U), FREQ_100MHZ); 385 csht = ((csht - 1U) << QSPI_DCR_CSHT_SHIFT) & QSPI_DCR_CSHT_MASK; 386 387 ret = stm32_qspi_wait_for_not_busy(); 388 if (ret != 0) { 389 return ret; 390 } 391 392 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_PRESCALER_MASK, 393 prescaler << QSPI_CR_PRESCALER_SHIFT); 394 395 mmio_clrsetbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CSHT_MASK, csht); 396 397 VERBOSE("%s: speed=%lu\n", __func__, qspi_clk / (prescaler + 1U)); 398 399 return 0; 400 } 401 402 static int stm32_qspi_set_mode(unsigned int mode) 403 { 404 int ret; 405 406 ret = stm32_qspi_wait_for_not_busy(); 407 if (ret != 0) { 408 return ret; 409 } 410 411 if ((mode & SPI_CS_HIGH) != 0U) { 412 return -ENODEV; 413 } 414 415 if (((mode & SPI_CPHA) != 0U) && ((mode & SPI_CPOL) != 0U)) { 416 mmio_setbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE); 417 } else if (((mode & SPI_CPHA) == 0U) && ((mode & SPI_CPOL) == 0U)) { 418 mmio_clrbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE); 419 } else { 420 return -ENODEV; 421 } 422 423 VERBOSE("%s: mode=0x%x\n", __func__, mode); 424 425 if ((mode & SPI_RX_QUAD) != 0U) { 426 VERBOSE("rx: quad\n"); 427 } else if ((mode & SPI_RX_DUAL) != 0U) { 428 VERBOSE("rx: dual\n"); 429 } else { 430 VERBOSE("rx: single\n"); 431 } 432 433 if ((mode & SPI_TX_QUAD) != 0U) { 434 VERBOSE("tx: quad\n"); 435 } else if ((mode & SPI_TX_DUAL) != 0U) { 436 VERBOSE("tx: dual\n"); 437 } else { 438 VERBOSE("tx: single\n"); 439 } 440 441 return 0; 442 } 443 444 static const struct spi_bus_ops stm32_qspi_bus_ops = { 445 .claim_bus = stm32_qspi_claim_bus, 446 .release_bus = stm32_qspi_release_bus, 447 .set_speed = stm32_qspi_set_speed, 448 .set_mode = stm32_qspi_set_mode, 449 .exec_op = stm32_qspi_exec_op, 450 }; 451 452 int stm32_qspi_init(void) 453 { 454 size_t size; 455 int qspi_node; 456 struct dt_node_info info; 457 void *fdt = NULL; 458 int ret; 459 460 if (fdt_get_address(&fdt) == 0) { 461 return -FDT_ERR_NOTFOUND; 462 } 463 464 qspi_node = dt_get_node(&info, -1, DT_QSPI_COMPAT); 465 if (qspi_node < 0) { 466 ERROR("No QSPI ctrl found\n"); 467 return -FDT_ERR_NOTFOUND; 468 } 469 470 if (info.status == DT_DISABLED) { 471 return -FDT_ERR_NOTFOUND; 472 } 473 474 ret = fdt_get_reg_props_by_name(fdt, qspi_node, "qspi", 475 &stm32_qspi.reg_base, &size); 476 if (ret != 0) { 477 return ret; 478 } 479 480 ret = fdt_get_reg_props_by_name(fdt, qspi_node, "qspi_mm", 481 &stm32_qspi.mm_base, 482 &stm32_qspi.mm_size); 483 if (ret != 0) { 484 return ret; 485 } 486 487 if (dt_set_pinctrl_config(qspi_node) != 0) { 488 return -FDT_ERR_BADVALUE; 489 } 490 491 if ((info.clock < 0) || (info.reset < 0)) { 492 return -FDT_ERR_BADVALUE; 493 } 494 495 stm32_qspi.clock_id = (unsigned long)info.clock; 496 stm32_qspi.reset_id = (unsigned int)info.reset; 497 498 clk_enable(stm32_qspi.clock_id); 499 500 ret = stm32mp_reset_assert(stm32_qspi.reset_id, TIMEOUT_US_1_MS); 501 if (ret != 0) { 502 panic(); 503 } 504 ret = stm32mp_reset_deassert(stm32_qspi.reset_id, TIMEOUT_US_1_MS); 505 if (ret != 0) { 506 panic(); 507 } 508 509 mmio_write_32(qspi_base() + QSPI_CR, QSPI_CR_SSHIFT); 510 mmio_write_32(qspi_base() + QSPI_DCR, QSPI_DCR_FSIZE_MASK); 511 512 return spi_mem_init_slave(fdt, qspi_node, &stm32_qspi_bus_ops); 513 }; 514