1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #include <assert.h> 9 10 #include <arch.h> 11 #include <bl31/interrupt_mgmt.h> 12 #include <caam.h> 13 #include <cassert.h> 14 #include <ccn.h> 15 #include <common/debug.h> 16 #include <dcfg.h> 17 #ifdef I2C_INIT 18 #include <i2c.h> 19 #endif 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <ls_interconnect.h> 23 #ifdef POLICY_FUSE_PROVISION 24 #include <nxp_gpio.h> 25 #endif 26 #if TRUSTED_BOARD_BOOT 27 #include <nxp_smmu.h> 28 #endif 29 #include <nxp_timer.h> 30 #include <plat_console.h> 31 #include <plat_gic.h> 32 #include <plat_tzc400.h> 33 #include <pmu.h> 34 #if defined(NXP_SFP_ENABLED) 35 #include <sfp.h> 36 #endif 37 38 #include <errata.h> 39 #include <ls_interrupt_mgmt.h> 40 #include "plat_common.h" 41 #ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA 42 #include <plat_nv_storage.h> 43 #endif 44 #ifdef NXP_WARM_BOOT 45 #include <plat_warm_rst.h> 46 #endif 47 #include "platform_def.h" 48 #include "soc.h" 49 50 static struct soc_type soc_list[] = { 51 /* SoC LX2160A */ 52 SOC_ENTRY(LX2160A, LX2160A, 8, 2), 53 SOC_ENTRY(LX2160E, LX2160E, 8, 2), 54 SOC_ENTRY(LX2160C, LX2160C, 8, 2), 55 SOC_ENTRY(LX2160N, LX2160N, 8, 2), 56 SOC_ENTRY(LX2080A, LX2080A, 8, 1), 57 SOC_ENTRY(LX2080E, LX2080E, 8, 1), 58 SOC_ENTRY(LX2080C, LX2080C, 8, 1), 59 SOC_ENTRY(LX2080N, LX2080N, 8, 1), 60 SOC_ENTRY(LX2120A, LX2120A, 6, 2), 61 SOC_ENTRY(LX2120E, LX2120E, 6, 2), 62 SOC_ENTRY(LX2120C, LX2120C, 6, 2), 63 SOC_ENTRY(LX2120N, LX2120N, 6, 2), 64 /* SoC LX2162A */ 65 SOC_ENTRY(LX2162A, LX2162A, 8, 2), 66 SOC_ENTRY(LX2162E, LX2162E, 8, 2), 67 SOC_ENTRY(LX2162C, LX2162C, 8, 2), 68 SOC_ENTRY(LX2162N, LX2162N, 8, 2), 69 SOC_ENTRY(LX2082A, LX2082A, 8, 1), 70 SOC_ENTRY(LX2082E, LX2082E, 8, 1), 71 SOC_ENTRY(LX2082C, LX2082C, 8, 1), 72 SOC_ENTRY(LX2082N, LX2082N, 8, 1), 73 SOC_ENTRY(LX2122A, LX2122A, 6, 2), 74 SOC_ENTRY(LX2122E, LX2122E, 6, 2), 75 SOC_ENTRY(LX2122C, LX2122C, 6, 2), 76 SOC_ENTRY(LX2122N, LX2122N, 6, 2), 77 }; 78 79 static dcfg_init_info_t dcfg_init_data = { 80 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 81 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 82 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 83 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 84 }; 85 static const unsigned char master_to_6rn_id_map[] = { 86 PLAT_6CLUSTER_TO_CCN_ID_MAP 87 }; 88 89 static const unsigned char master_to_rn_id_map[] = { 90 PLAT_CLUSTER_TO_CCN_ID_MAP 91 }; 92 93 CASSERT(ARRAY_SIZE(master_to_rn_id_map) == NUMBER_OF_CLUSTERS, 94 assert_invalid_cluster_count_for_ccn_variant); 95 96 static const ccn_desc_t plat_six_cluster_ccn_desc = { 97 .periphbase = NXP_CCN_ADDR, 98 .num_masters = ARRAY_SIZE(master_to_6rn_id_map), 99 .master_to_rn_id_map = master_to_6rn_id_map 100 }; 101 102 static const ccn_desc_t plat_ccn_desc = { 103 .periphbase = NXP_CCN_ADDR, 104 .num_masters = ARRAY_SIZE(master_to_rn_id_map), 105 .master_to_rn_id_map = master_to_rn_id_map 106 }; 107 108 /****************************************************************************** 109 * Function returns the base counter frequency 110 * after reading the first entry at CNTFID0 (0x20 offset). 111 * 112 * Function is used by: 113 * 1. ARM common code for PSCI management. 114 * 2. ARM Generic Timer init. 115 * 116 *****************************************************************************/ 117 unsigned int plat_get_syscnt_freq2(void) 118 { 119 unsigned int counter_base_frequency; 120 /* 121 * Below register specifies the base frequency of the system counter. 122 * As per NXP Board Manuals: 123 * The system counter always works with SYS_REF_CLK/4 frequency clock. 124 * 125 * 126 */ 127 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); 128 129 return counter_base_frequency; 130 } 131 132 #ifdef IMAGE_BL2 133 134 #ifdef POLICY_FUSE_PROVISION 135 static gpio_init_info_t gpio_init_data = { 136 .gpio1_base_addr = NXP_GPIO1_ADDR, 137 .gpio2_base_addr = NXP_GPIO2_ADDR, 138 .gpio3_base_addr = NXP_GPIO3_ADDR, 139 .gpio4_base_addr = NXP_GPIO4_ADDR, 140 }; 141 #endif 142 143 static void soc_interconnect_config(void) 144 { 145 unsigned long long val = 0x0U; 146 uint8_t num_clusters, cores_per_cluster; 147 148 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), 149 &num_clusters, &cores_per_cluster); 150 151 if (num_clusters == 6U) { 152 ccn_init(&plat_six_cluster_ccn_desc); 153 } else { 154 ccn_init(&plat_ccn_desc); 155 } 156 157 /* 158 * Enable Interconnect coherency for the primary CPU's cluster. 159 */ 160 plat_ls_interconnect_enter_coherency(num_clusters); 161 162 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET); 163 val |= (1 << 17); 164 ccn_write_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET, val); 165 166 /* PCIe is Connected to RN-I 17 which is connected to HN-I 13. */ 167 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET); 168 val |= (1 << 17); 169 ccn_write_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET, val); 170 171 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET); 172 val |= SERIALIZE_DEV_nGnRnE_WRITES; 173 ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val); 174 175 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET); 176 val &= ~(ENABLE_RESERVE_BIT53); 177 val |= SERIALIZE_DEV_nGnRnE_WRITES; 178 ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val); 179 180 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET); 181 val &= ~(HNI_POS_EN); 182 ccn_write_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET, val); 183 184 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET); 185 val &= ~(HNI_POS_EN); 186 ccn_write_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET, val); 187 188 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET); 189 val &= ~(POS_EARLY_WR_COMP_EN); 190 ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val); 191 192 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET); 193 val &= ~(POS_EARLY_WR_COMP_EN); 194 ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val); 195 196 #if POLICY_PERF_WRIOP 197 uint16_t wriop_rni = 0U; 198 199 if (POLICY_PERF_WRIOP == 1) { 200 wriop_rni = 7U; 201 } else if (POLICY_PERF_WRIOP == 2) { 202 wriop_rni = 23U; 203 } else { 204 ERROR("Incorrect WRIOP selected.\n"); 205 panic(); 206 } 207 208 val = ccn_read_node_reg(NODE_TYPE_RNI, wriop_rni, 209 SA_AUX_CTRL_REG_OFFSET); 210 val |= ENABLE_WUO; 211 ccn_write_node_reg(NODE_TYPE_HNI, wriop_rni, SA_AUX_CTRL_REG_OFFSET, 212 val); 213 #else 214 val = ccn_read_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET); 215 val |= ENABLE_WUO; 216 ccn_write_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET, val); 217 #endif 218 } 219 220 221 void soc_preload_setup(void) 222 { 223 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 224 #if defined(NXP_WARM_BOOT) 225 bool warm_reset = is_warm_boot(); 226 #endif 227 info_dram_regions->total_dram_size = 228 #if defined(NXP_WARM_BOOT) 229 init_ddr(warm_reset); 230 #else 231 init_ddr(); 232 #endif 233 } 234 235 /******************************************************************************* 236 * This function implements soc specific erratas 237 * This is called before DDR is initialized or MMU is enabled 238 ******************************************************************************/ 239 void soc_early_init(void) 240 { 241 dcfg_init(&dcfg_init_data); 242 #ifdef POLICY_FUSE_PROVISION 243 gpio_init(&gpio_init_data); 244 sec_init(NXP_CAAM_ADDR); 245 #endif 246 #if LOG_LEVEL > 0 247 /* Initialize the console to provide early debug support */ 248 plat_console_init(NXP_CONSOLE_ADDR, 249 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 250 #endif 251 252 enable_timer_base_to_cluster(NXP_PMU_ADDR); 253 soc_interconnect_config(); 254 255 enum boot_device dev = get_boot_dev(); 256 /* Mark the buffer for SD in OCRAM as non secure. 257 * The buffer is assumed to be at end of OCRAM for 258 * the logic below to calculate TZPC programming 259 */ 260 if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) { 261 /* Calculate the region in OCRAM which is secure 262 * The buffer for SD needs to be marked non-secure 263 * to allow SD to do DMA operations on it 264 */ 265 uint32_t secure_region = (NXP_OCRAM_SIZE 266 - NXP_SD_BLOCK_BUF_SIZE); 267 uint32_t mask = secure_region/TZPC_BLOCK_SIZE; 268 269 mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask); 270 271 /* Add the entry for buffer in MMU Table */ 272 mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR, 273 NXP_SD_BLOCK_BUF_SIZE, 274 MT_DEVICE | MT_RW | MT_NS); 275 } 276 277 soc_errata(); 278 279 #if (TRUSTED_BOARD_BOOT) || defined(POLICY_FUSE_PROVISION) 280 sfp_init(NXP_SFP_ADDR); 281 #endif 282 283 #if TRUSTED_BOARD_BOOT 284 uint32_t mode; 285 286 /* For secure boot disable SMMU. 287 * Later when platform security policy comes in picture, 288 * this might get modified based on the policy 289 */ 290 if (check_boot_mode_secure(&mode) == true) { 291 bypass_smmu(NXP_SMMU_ADDR); 292 } 293 294 /* For Mbedtls currently crypto is not supported via CAAM 295 * enable it when that support is there. In tbbr.mk 296 * the CAAM_INTEG is set as 0. 297 */ 298 299 #ifndef MBEDTLS_X509 300 /* Initialize the crypto accelerator if enabled */ 301 if (is_sec_enabled() == false) 302 INFO("SEC is disabled.\n"); 303 else 304 sec_init(NXP_CAAM_ADDR); 305 #endif 306 #endif 307 308 /* 309 * Initialize system level generic timer for Layerscape Socs. 310 */ 311 delay_timer_init(NXP_TIMER_ADDR); 312 i2c_init(NXP_I2C_ADDR); 313 } 314 315 void soc_bl2_prepare_exit(void) 316 { 317 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 318 set_sfp_wr_disable(); 319 #endif 320 } 321 322 /***************************************************************************** 323 * This function returns the boot device based on RCW_SRC 324 ****************************************************************************/ 325 enum boot_device get_boot_dev(void) 326 { 327 enum boot_device src = BOOT_DEVICE_NONE; 328 uint32_t porsr1; 329 uint32_t rcw_src; 330 331 porsr1 = read_reg_porsr1(); 332 333 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 334 335 switch (rcw_src) { 336 case FLEXSPI_NOR: 337 src = BOOT_DEVICE_FLEXSPI_NOR; 338 INFO("RCW BOOT SRC is FLEXSPI NOR\n"); 339 break; 340 case FLEXSPI_NAND2K_VAL: 341 case FLEXSPI_NAND4K_VAL: 342 INFO("RCW BOOT SRC is FLEXSPI NAND\n"); 343 src = BOOT_DEVICE_FLEXSPI_NAND; 344 break; 345 case SDHC1_VAL: 346 src = BOOT_DEVICE_EMMC; 347 INFO("RCW BOOT SRC is SD\n"); 348 break; 349 case SDHC2_VAL: 350 src = BOOT_DEVICE_SDHC2_EMMC; 351 INFO("RCW BOOT SRC is EMMC\n"); 352 break; 353 default: 354 break; 355 } 356 357 return src; 358 } 359 360 361 void soc_mem_access(void) 362 { 363 const devdisr5_info_t *devdisr5_info = get_devdisr5_info(); 364 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 365 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; 366 int dram_idx, index = 0U; 367 368 for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions; 369 dram_idx++) { 370 if (info_dram_regions->region[dram_idx].size == 0) { 371 ERROR("DDR init failure, or"); 372 ERROR("DRAM regions not populated correctly.\n"); 373 break; 374 } 375 376 index = populate_tzc400_reg_list(tzc400_reg_list, 377 dram_idx, index, 378 info_dram_regions->region[dram_idx].addr, 379 info_dram_regions->region[dram_idx].size, 380 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 381 } 382 383 if (devdisr5_info->ddrc1_present != 0) { 384 INFO("DDR Controller 1.\n"); 385 mem_access_setup(NXP_TZC_ADDR, index, 386 tzc400_reg_list); 387 mem_access_setup(NXP_TZC3_ADDR, index, 388 tzc400_reg_list); 389 } 390 if (devdisr5_info->ddrc2_present != 0) { 391 INFO("DDR Controller 2.\n"); 392 mem_access_setup(NXP_TZC2_ADDR, index, 393 tzc400_reg_list); 394 mem_access_setup(NXP_TZC4_ADDR, index, 395 tzc400_reg_list); 396 } 397 } 398 399 #else 400 const unsigned char _power_domain_tree_desc[] = {1, 8, 2, 2, 2, 2, 2, 2, 2, 2}; 401 402 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 403 assert_invalid_lx2160a_cluster_count); 404 405 /****************************************************************************** 406 * This function returns the SoC topology 407 ****************************************************************************/ 408 409 const unsigned char *plat_get_power_domain_tree_desc(void) 410 { 411 412 return _power_domain_tree_desc; 413 } 414 415 /******************************************************************************* 416 * This function returns the core count within the cluster corresponding to 417 * `mpidr`. 418 ******************************************************************************/ 419 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 420 { 421 return CORES_PER_CLUSTER; 422 } 423 424 425 void soc_early_platform_setup2(void) 426 { 427 dcfg_init(&dcfg_init_data); 428 /* 429 * Initialize system level generic timer for Socs 430 */ 431 delay_timer_init(NXP_TIMER_ADDR); 432 433 #if LOG_LEVEL > 0 434 /* Initialize the console to provide early debug support */ 435 plat_console_init(NXP_CONSOLE_ADDR, 436 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 437 #endif 438 } 439 440 void soc_platform_setup(void) 441 { 442 /* Initialize the GIC driver, cpu and distributor interfaces */ 443 static uintptr_t target_mask_array[PLATFORM_CORE_COUNT]; 444 static interrupt_prop_t ls_interrupt_props[] = { 445 PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S), 446 PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0) 447 }; 448 449 plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR, 450 PLATFORM_CORE_COUNT, 451 ls_interrupt_props, 452 ARRAY_SIZE(ls_interrupt_props), 453 target_mask_array, 454 plat_core_pos); 455 456 plat_ls_gic_init(); 457 enable_init_timer(); 458 #ifdef LS_SYS_TIMCTL_BASE 459 ls_configure_sys_timer(LS_SYS_TIMCTL_BASE, 460 LS_CONFIG_CNTACR, 461 PLAT_LS_NSTIMER_FRAME_ID); 462 #endif 463 } 464 465 /******************************************************************************* 466 * This function initializes the soc from the BL31 module 467 ******************************************************************************/ 468 void soc_init(void) 469 { 470 uint8_t num_clusters, cores_per_cluster; 471 472 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), 473 &num_clusters, &cores_per_cluster); 474 475 /* low-level init of the soc */ 476 soc_init_start(); 477 _init_global_data(); 478 soc_init_percpu(); 479 _initialize_psci(); 480 481 if (ccn_get_part0_id(NXP_CCN_ADDR) != CCN_508_PART0_ID) { 482 ERROR("Unrecognized CCN variant detected."); 483 ERROR("Only CCN-508 is supported\n"); 484 panic(); 485 } 486 487 if (num_clusters == 6U) { 488 ccn_init(&plat_six_cluster_ccn_desc); 489 } else { 490 ccn_init(&plat_ccn_desc); 491 } 492 493 plat_ls_interconnect_enter_coherency(num_clusters); 494 495 /* Set platform security policies */ 496 _set_platform_security(); 497 498 /* make sure any parallel init tasks are finished */ 499 soc_init_finish(); 500 501 /* Initialize the crypto accelerator if enabled */ 502 if (is_sec_enabled() == false) { 503 INFO("SEC is disabled.\n"); 504 } else { 505 sec_init(NXP_CAAM_ADDR); 506 } 507 508 } 509 510 #ifdef NXP_WDOG_RESTART 511 static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags, 512 void *handle, void *cookie) 513 { 514 uint8_t data = WDOG_RESET_FLAG; 515 516 wr_nv_app_data(WDT_RESET_FLAG_OFFSET, 517 (uint8_t *)&data, sizeof(data)); 518 519 mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT); 520 521 return 0; 522 } 523 #endif 524 525 void soc_runtime_setup(void) 526 { 527 528 #ifdef NXP_WDOG_RESTART 529 request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler); 530 #endif 531 } 532 #endif 533