1 /* 2 * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net> 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <common/debug.h> 11 #include <drivers/console.h> 12 #include <drivers/generic_delay_timer.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_mmu_helpers.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 #include <plat/common/platform.h> 17 18 #include "msm8916_gicv2.h" 19 #include <msm8916_mmap.h> 20 #include <platform_def.h> 21 #include <uartdm_console.h> 22 23 static const mmap_region_t msm8916_mmap[] = { 24 MAP_REGION_FLAT(PCNOC_BASE, PCNOC_SIZE, 25 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), 26 MAP_REGION_FLAT(APCS_BASE, APCS_SIZE, 27 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), 28 {}, 29 }; 30 31 static struct { 32 entry_point_info_t bl32; 33 entry_point_info_t bl33; 34 } image_ep_info = { 35 /* BL32 entry point */ 36 SET_STATIC_PARAM_HEAD(bl32, PARAM_EP, VERSION_1, 37 entry_point_info_t, SECURE), 38 .bl32.pc = BL32_BASE, 39 40 /* BL33 entry point */ 41 SET_STATIC_PARAM_HEAD(bl33, PARAM_EP, VERSION_1, 42 entry_point_info_t, NON_SECURE), 43 .bl33.pc = PRELOADED_BL33_BASE, 44 .bl33.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), 45 }; 46 47 static console_t console; 48 49 unsigned int plat_get_syscnt_freq2(void) 50 { 51 return PLAT_SYSCNT_FREQ; 52 } 53 54 #define CLK_ENABLE BIT_32(0) 55 #define CLK_OFF BIT_32(31) 56 57 #define GPIO_BLSP_UART2_TX 4 58 #define GPIO_BLSP_UART2_RX 5 59 #define GPIO_CFG_FUNC_BLSP_UART2 (U(0x2) << 2) 60 #define GPIO_CFG_DRV_STRENGTH_16MA (U(0x7) << 6) 61 62 #define GCC_BLSP1_AHB_CBCR (GCC_BASE + 0x01008) 63 #define GCC_BLSP1_UART2_APPS_CBCR (GCC_BASE + 0x0302c) 64 #define GCC_APCS_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x45004) 65 #define BLSP1_AHB_CLK_ENA BIT_32(10) 66 67 /* 68 * The previous boot stage seems to disable most of the UART setup before exit 69 * so it must be enabled here again before the UART console can be used. 70 */ 71 static void msm8916_enable_blsp_uart2(void) 72 { 73 /* Route GPIOs to BLSP UART2 */ 74 mmio_write_32(TLMM_GPIO_CFG(GPIO_BLSP_UART2_TX), 75 GPIO_CFG_FUNC_BLSP_UART2 | GPIO_CFG_DRV_STRENGTH_16MA); 76 mmio_write_32(TLMM_GPIO_CFG(GPIO_BLSP_UART2_RX), 77 GPIO_CFG_FUNC_BLSP_UART2 | GPIO_CFG_DRV_STRENGTH_16MA); 78 79 /* Enable AHB clock */ 80 mmio_setbits_32(GCC_APCS_CLOCK_BRANCH_ENA_VOTE, BLSP1_AHB_CLK_ENA); 81 while (mmio_read_32(GCC_BLSP1_AHB_CBCR) & CLK_OFF) 82 ; 83 84 /* Enable BLSP UART2 clock */ 85 mmio_setbits_32(GCC_BLSP1_UART2_APPS_CBCR, CLK_ENABLE); 86 while (mmio_read_32(GCC_BLSP1_UART2_APPS_CBCR) & CLK_OFF) 87 ; 88 } 89 90 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 91 u_register_t arg2, u_register_t arg3) 92 { 93 /* Initialize the debug console as early as possible */ 94 msm8916_enable_blsp_uart2(); 95 console_uartdm_register(&console, BLSP_UART2_BASE); 96 } 97 98 void bl31_plat_arch_setup(void) 99 { 100 mmap_add_region(BL31_BASE, BL31_BASE, BL31_END - BL31_BASE, 101 MT_RW_DATA | MT_SECURE); 102 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 103 BL_CODE_END - BL_CODE_BASE, 104 MT_CODE | MT_SECURE); 105 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 106 BL_RO_DATA_END - BL_RO_DATA_BASE, 107 MT_RO_DATA | MT_SECURE); 108 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 109 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 110 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER); 111 112 mmap_add(msm8916_mmap); 113 init_xlat_tables(); 114 enable_mmu_el3(0); 115 } 116 117 static void msm8916_configure_timer(void) 118 { 119 /* Set timer frequency */ 120 mmio_write_32(APCS_QTMR + CNTCTLBASE_CNTFRQ, plat_get_syscnt_freq2()); 121 122 /* Make frame 0 available to non-secure world */ 123 mmio_write_32(APCS_QTMR + CNTNSAR, BIT_32(CNTNSAR_NS_SHIFT(0))); 124 mmio_write_32(APCS_QTMR + CNTACR_BASE(0), 125 BIT_32(CNTACR_RPCT_SHIFT) | BIT_32(CNTACR_RVCT_SHIFT) | 126 BIT_32(CNTACR_RFRQ_SHIFT) | BIT_32(CNTACR_RVOFF_SHIFT) | 127 BIT_32(CNTACR_RWVT_SHIFT) | BIT_32(CNTACR_RWPT_SHIFT)); 128 } 129 130 /* 131 * The APCS register regions always start with a SECURE register that should 132 * be cleared to 0 to only allow secure access. Since BL31 handles most of 133 * the CPU power management, most of them can be cleared to secure access only. 134 */ 135 #define APCS_GLB_SECURE_STS_NS BIT_32(0) 136 #define APCS_GLB_SECURE_PWR_NS BIT_32(1) 137 #define APCS_BOOT_START_ADDR_SEC (APCS_CFG + 0x04) 138 #define REMAP_EN BIT_32(0) 139 #define APCS_AA64NAA32_REG (APCS_CFG + 0x0c) 140 141 static void msm8916_configure_cpu_pm(void) 142 { 143 unsigned int cpu; 144 145 /* Disallow non-secure access to boot remapper / TCM registers */ 146 mmio_write_32(APCS_CFG, 0); 147 148 /* 149 * Disallow non-secure access to power management registers. 150 * However, allow STS and PWR since those also seem to control access 151 * to CPU frequency related registers (e.g. APCS_CMD_RCGR). If these 152 * bits are not set, CPU frequency control fails in the non-secure world. 153 */ 154 mmio_write_32(APCS_GLB, APCS_GLB_SECURE_STS_NS | APCS_GLB_SECURE_PWR_NS); 155 156 /* Disallow non-secure access to L2 SAW2 */ 157 mmio_write_32(APCS_L2_SAW2, 0); 158 159 /* Disallow non-secure access to CPU ACS and SAW2 */ 160 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { 161 mmio_write_32(APCS_ALIAS_ACS(cpu), 0); 162 mmio_write_32(APCS_ALIAS_SAW2(cpu), 0); 163 } 164 165 /* Make sure all further warm boots end up in BL31 and aarch64 state */ 166 CASSERT((BL31_BASE & 0xffff) == 0, assert_bl31_base_64k_aligned); 167 mmio_write_32(APCS_BOOT_START_ADDR_SEC, BL31_BASE | REMAP_EN); 168 mmio_write_32(APCS_AA64NAA32_REG, 1); 169 } 170 171 /* 172 * MSM8916 has a special "interrupt aggregation logic" in the APPS SMMU, 173 * which allows routing context bank interrupts to one of 3 interrupt numbers 174 * ("TZ/HYP/NS"). Route all interrupts to the non-secure interrupt number 175 * by default to avoid special setup on the non-secure side. 176 */ 177 #define GCC_SMMU_CFG_CBCR (GCC_BASE + 0x12038) 178 #define GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x4500c) 179 #define SMMU_CFG_CLK_ENA BIT_32(12) 180 #define APPS_SMMU_INTR_SEL_NS (APPS_SMMU_QCOM + 0x2000) 181 #define APPS_SMMU_INTR_SEL_NS_EN_ALL U(0xffffffff) 182 183 static void msm8916_configure_smmu(void) 184 { 185 /* Enable SMMU configuration clock to enable register access */ 186 mmio_setbits_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA); 187 while (mmio_read_32(GCC_SMMU_CFG_CBCR) & CLK_OFF) 188 ; 189 190 /* Route all context bank interrupts to non-secure interrupt */ 191 mmio_write_32(APPS_SMMU_INTR_SEL_NS, APPS_SMMU_INTR_SEL_NS_EN_ALL); 192 193 /* Disable configuration clock again */ 194 mmio_clrbits_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA); 195 } 196 197 void bl31_platform_setup(void) 198 { 199 INFO("BL31: Platform setup start\n"); 200 generic_delay_timer_init(); 201 msm8916_configure_timer(); 202 msm8916_gicv2_init(); 203 msm8916_configure_cpu_pm(); 204 msm8916_configure_smmu(); 205 INFO("BL31: Platform setup done\n"); 206 } 207 208 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 209 { 210 switch (type) { 211 case SECURE: 212 return &image_ep_info.bl32; 213 case NON_SECURE: 214 return &image_ep_info.bl33; 215 default: 216 assert(sec_state_is_valid(type)); 217 return NULL; 218 } 219 } 220