1 /* 2 * Copyright 2019-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <gpc.h> 23 #include <imx_aipstz.h> 24 #include <imx_uart.h> 25 #include <imx_rdc.h> 26 #include <imx8m_caam.h> 27 #include <imx8m_csu.h> 28 #include <platform_def.h> 29 #include <plat_imx8.h> 30 31 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 32 33 static const mmap_region_t imx_mmap[] = { 34 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, {0}, 35 }; 36 37 static const struct aipstz_cfg aipstz[] = { 38 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 39 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 41 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 42 {0}, 43 }; 44 45 static const struct imx_rdc_cfg rdc[] = { 46 /* Master domain assignment */ 47 RDC_MDAn(RDC_MDA_M7, DID1), 48 49 /* peripherals domain permission */ 50 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W), 51 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 52 53 /* memory region */ 54 RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff), 55 RDC_MEM_REGIONn(17, 0x0, 0x0, 0xff), 56 RDC_MEM_REGIONn(18, 0x0, 0x0, 0xff), 57 58 /* Sentinel */ 59 {0}, 60 }; 61 62 static const struct imx_csu_cfg csu_cfg[] = { 63 /* peripherals csl setting */ 64 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 65 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 66 67 /* master HP0~1 */ 68 69 /* SA setting */ 70 71 /* HP control setting */ 72 73 /* Sentinel */ 74 {0} 75 }; 76 77 78 static entry_point_info_t bl32_image_ep_info; 79 static entry_point_info_t bl33_image_ep_info; 80 81 /* get SPSR for BL33 entry */ 82 static uint32_t get_spsr_for_bl33_entry(void) 83 { 84 unsigned long el_status; 85 unsigned long mode; 86 uint32_t spsr; 87 88 /* figure out what mode we enter the non-secure world */ 89 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 90 el_status &= ID_AA64PFR0_ELX_MASK; 91 92 mode = (el_status) ? MODE_EL2 : MODE_EL1; 93 94 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 95 return spsr; 96 } 97 98 static void bl31_tzc380_setup(void) 99 { 100 unsigned int val; 101 102 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 103 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 104 return; 105 106 tzc380_init(IMX_TZASC_BASE); 107 108 /* 109 * Need to substact offset 0x40000000 from CPU address when 110 * programming tzasc region for i.mx8mn. 111 */ 112 113 /* Enable 1G-5G S/NS RW */ 114 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 115 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 116 } 117 118 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 119 u_register_t arg2, u_register_t arg3) 120 { 121 static console_t console; 122 unsigned int val; 123 int i; 124 125 /* Enable CSU NS access permission */ 126 for (i = 0; i < 64; i++) { 127 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 128 } 129 130 imx_aipstz_init(aipstz); 131 132 imx_rdc_init(rdc); 133 134 imx_csu_init(csu_cfg); 135 136 /* config the ocram memory range for secure access */ 137 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4c1); 138 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 139 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 140 141 imx8m_caam_init(); 142 143 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 144 IMX_CONSOLE_BAUDRATE, &console); 145 /* This console is only used for boot stage */ 146 console_set_scope(&console, CONSOLE_FLAG_BOOT); 147 148 /* 149 * tell BL3-1 where the non-secure software image is located 150 * and the entry state information. 151 */ 152 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 153 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 154 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 155 156 #if defined(SPD_opteed) || defined(SPD_trusty) 157 /* Populate entry point information for BL32 */ 158 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 159 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 160 bl32_image_ep_info.pc = BL32_BASE; 161 bl32_image_ep_info.spsr = 0; 162 163 /* Pass TEE base and size to bl33 */ 164 bl33_image_ep_info.args.arg1 = BL32_BASE; 165 bl33_image_ep_info.args.arg2 = BL32_SIZE; 166 167 #ifdef SPD_trusty 168 bl32_image_ep_info.args.arg0 = BL32_SIZE; 169 bl32_image_ep_info.args.arg1 = BL32_BASE; 170 #else 171 /* Make sure memory is clean */ 172 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 173 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 174 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 175 #endif 176 #endif 177 178 bl31_tzc380_setup(); 179 } 180 181 void bl31_plat_arch_setup(void) 182 { 183 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 184 MT_MEMORY | MT_RW | MT_SECURE); 185 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 186 MT_MEMORY | MT_RO | MT_SECURE); 187 #if USE_COHERENT_MEM 188 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 189 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 190 MT_DEVICE | MT_RW | MT_SECURE); 191 #endif 192 193 /* Map TEE memory */ 194 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); 195 196 mmap_add(imx_mmap); 197 198 init_xlat_tables(); 199 200 enable_mmu_el3(0); 201 } 202 203 void bl31_platform_setup(void) 204 { 205 generic_delay_timer_init(); 206 207 /* select the CKIL source to 32K OSC */ 208 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 209 210 plat_gic_driver_init(); 211 plat_gic_init(); 212 213 imx_gpc_init(); 214 } 215 216 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 217 { 218 if (type == NON_SECURE) 219 return &bl33_image_ep_info; 220 if (type == SECURE) 221 return &bl32_image_ep_info; 222 223 return NULL; 224 } 225 226 unsigned int plat_get_syscnt_freq2(void) 227 { 228 return COUNTER_FREQUENCY; 229 } 230 231 #ifdef SPD_trusty 232 void plat_trusty_set_boot_args(aapcs64_params_t *args) 233 { 234 args->arg0 = BL32_SIZE; 235 args->arg1 = BL32_BASE; 236 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 237 } 238 #endif 239