1# 2# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 28# progbits limit. We need a way to build all useful configurations while waiting 29# on the fvp to increase its SRAM size. The problem is twofild: 30# 1. the cleanup that introduced these enables cleaned up tf-a a little too 31# well and things that previously (incorrectly) were enabled, no longer are. 32# A bunch of CI configs build subtly incorrectly and this combo makes it 33# necessary to forcefully and unconditionally enable them here. 34# 2. the progbits limit is exceeded only when the tsp is involved. However, 35# there are tsp CI configs that run on very high architecture revisions so 36# disabling everything isn't an option. 37# The fix is to enable everything, as before. When the tsp is included, though, 38# we need to slim the size down. In that case, disable all optional features, 39# that will not be present in CI when the tsp is. 40# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 41# for it. 42# TODO: make all of this unconditional (or only base the condition on 43# ARM_ARCH_* when the makefile supports it). 44ifneq (${DRTM_SUPPORT}, 1) 45ifneq (${SPD}, tspd) 46 ENABLE_FEAT_AMU := 2 47 ENABLE_FEAT_AMUv1p1 := 2 48 ENABLE_FEAT_HCX := 2 49 ENABLE_MPAM_FOR_LOWER_ELS := 2 50 ENABLE_FEAT_RNG := 2 51 ENABLE_FEAT_TWED := 2 52 ENABLE_FEAT_GCS := 2 53ifeq (${ARCH}, aarch64) 54ifneq (${SPD}, spmd) 55ifeq (${SPM_MM}, 0) 56ifeq (${ENABLE_RME}, 0) 57ifeq (${CTX_INCLUDE_FPREGS}, 0) 58 ENABLE_SME_FOR_NS := 2 59 ENABLE_SME2_FOR_NS := 2 60endif 61endif 62endif 63endif 64endif 65endif 66 67# enable unconditionally for all builds 68ifeq (${ARCH}, aarch64) 69ifeq (${ENABLE_RME},0) 70 ENABLE_BRBE_FOR_NS := 2 71endif 72endif 73ENABLE_TRBE_FOR_NS := 2 74ENABLE_SYS_REG_TRACE_FOR_NS := 2 75ENABLE_FEAT_CSV2_2 := 2 76ENABLE_FEAT_DIT := 2 77ENABLE_FEAT_PAN := 2 78ENABLE_FEAT_VHE := 2 79CTX_INCLUDE_NEVE_REGS := 2 80ENABLE_FEAT_SEL2 := 2 81ENABLE_TRF_FOR_NS := 2 82ENABLE_FEAT_ECV := 2 83ENABLE_FEAT_FGT := 2 84ENABLE_FEAT_TCR2 := 2 85ENABLE_FEAT_S2PIE := 2 86ENABLE_FEAT_S1PIE := 2 87ENABLE_FEAT_S2POE := 2 88ENABLE_FEAT_S1POE := 2 89endif 90 91# The FVP platform depends on this macro to build with correct GIC driver. 92$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 93 94# Pass FVP_CLUSTER_COUNT to the build system. 95$(eval $(call add_define,FVP_CLUSTER_COUNT)) 96 97# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 98$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 99 100# Pass FVP_MAX_PE_PER_CPU to the build system. 101$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 102 103# Pass FVP_GICR_REGION_PROTECTION to the build system. 104$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 105 106# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 107# choose the CCI driver , else the CCN driver 108ifeq ($(FVP_CLUSTER_COUNT), 0) 109$(error "Incorrect cluster count specified for FVP port") 110else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 111FVP_INTERCONNECT_DRIVER := FVP_CCI 112else 113FVP_INTERCONNECT_DRIVER := FVP_CCN 114endif 115 116$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 117 118# Choose the GIC sources depending upon the how the FVP will be invoked 119ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 120 121# The GIC model (GIC-600 or GIC-500) will be detected at runtime 122GICV3_SUPPORT_GIC600 := 1 123GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 124 125# Include GICv3 driver files 126include drivers/arm/gic/v3/gicv3.mk 127 128FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 129 plat/common/plat_gicv3.c \ 130 plat/arm/common/arm_gicv3.c 131 132 ifeq ($(filter 1,${RESET_TO_BL2} \ 133 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 134 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 135 endif 136 137else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 138 139# No GICv4 extension 140GIC_ENABLE_V4_EXTN := 0 141$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 142 143# Include GICv2 driver files 144include drivers/arm/gic/v2/gicv2.mk 145 146FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 147 plat/common/plat_gicv2.c \ 148 plat/arm/common/arm_gicv2.c 149 150FVP_DT_PREFIX := fvp-base-gicv2-psci 151else 152$(error "Incorrect GIC driver chosen on FVP port") 153endif 154 155ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 156FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 157else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 158FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 159 plat/arm/common/arm_ccn.c 160else 161$(error "Incorrect CCN driver chosen on FVP port") 162endif 163 164FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 165 plat/arm/board/fvp/fvp_security.c \ 166 plat/arm/common/arm_tzc400.c 167 168 169PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 170 -Iinclude/lib/psa 171 172 173PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 174 175FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 176 177ifeq (${ARCH}, aarch64) 178 179# select a different set of CPU files, depending on whether we compile for 180# hardware assisted coherency cores or not 181ifeq (${HW_ASSISTED_COHERENCY}, 0) 182# Cores used without DSU 183 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 184 lib/cpus/aarch64/cortex_a53.S \ 185 lib/cpus/aarch64/cortex_a57.S \ 186 lib/cpus/aarch64/cortex_a72.S \ 187 lib/cpus/aarch64/cortex_a73.S 188else 189# Cores used with DSU only 190 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 191 # AArch64-only cores 192 # TODO: add all cores to the appropriate lists 193 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 194 lib/cpus/aarch64/cortex_a65ae.S \ 195 lib/cpus/aarch64/cortex_a76.S \ 196 lib/cpus/aarch64/cortex_a76ae.S \ 197 lib/cpus/aarch64/cortex_a77.S \ 198 lib/cpus/aarch64/cortex_a78.S \ 199 lib/cpus/aarch64/cortex_a78c.S \ 200 lib/cpus/aarch64/cortex_a710.S \ 201 lib/cpus/aarch64/neoverse_n_common.S \ 202 lib/cpus/aarch64/neoverse_n1.S \ 203 lib/cpus/aarch64/neoverse_n2.S \ 204 lib/cpus/aarch64/neoverse_v1.S \ 205 lib/cpus/aarch64/neoverse_e1.S \ 206 lib/cpus/aarch64/cortex_x2.S 207 endif 208 # AArch64/AArch32 cores 209 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 210 lib/cpus/aarch64/cortex_a75.S 211endif 212 213else 214FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 215 lib/cpus/aarch32/cortex_a57.S 216endif 217 218BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 219 drivers/arm/sp805/sp805.c \ 220 drivers/delay_timer/delay_timer.c \ 221 drivers/io/io_semihosting.c \ 222 lib/semihosting/semihosting.c \ 223 lib/semihosting/${ARCH}/semihosting_call.S \ 224 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 225 plat/arm/board/fvp/fvp_bl1_setup.c \ 226 plat/arm/board/fvp/fvp_err.c \ 227 plat/arm/board/fvp/fvp_io_storage.c \ 228 ${FVP_CPU_LIBS} \ 229 ${FVP_INTERCONNECT_SOURCES} 230 231ifeq (${USE_SP804_TIMER},1) 232BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 233else 234BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 235endif 236 237 238BL2_SOURCES += drivers/arm/sp805/sp805.c \ 239 drivers/io/io_semihosting.c \ 240 lib/utils/mem_region.c \ 241 lib/semihosting/semihosting.c \ 242 lib/semihosting/${ARCH}/semihosting_call.S \ 243 plat/arm/board/fvp/fvp_bl2_setup.c \ 244 plat/arm/board/fvp/fvp_err.c \ 245 plat/arm/board/fvp/fvp_io_storage.c \ 246 plat/arm/common/arm_nor_psci_mem_protect.c \ 247 ${FVP_SECURITY_SOURCES} 248 249 250ifeq (${COT_DESC_IN_DTB},1) 251BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 252endif 253 254ifeq (${ENABLE_RME},1) 255BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 256 257BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 258 plat/arm/board/fvp/fvp_realm_attest_key.c 259 260# FVP platform does not support RSS, but it can leverage RSS APIs to 261# provide hardcoded token/key on request. 262BL31_SOURCES += lib/psa/delegated_attestation.c 263 264endif 265 266ifeq (${ENABLE_FEAT_RNG_TRAP},1) 267BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 268endif 269 270ifeq (${RESET_TO_BL2},1) 271BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 272 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 273 ${FVP_CPU_LIBS} \ 274 ${FVP_INTERCONNECT_SOURCES} 275endif 276 277ifeq (${USE_SP804_TIMER},1) 278BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 279endif 280 281BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 282 ${FVP_SECURITY_SOURCES} 283 284ifeq (${USE_SP804_TIMER},1) 285BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 286endif 287 288BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 289 drivers/arm/smmu/smmu_v3.c \ 290 drivers/delay_timer/delay_timer.c \ 291 drivers/cfi/v2m/v2m_flash.c \ 292 lib/utils/mem_region.c \ 293 plat/arm/board/fvp/fvp_bl31_setup.c \ 294 plat/arm/board/fvp/fvp_console.c \ 295 plat/arm/board/fvp/fvp_pm.c \ 296 plat/arm/board/fvp/fvp_topology.c \ 297 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 298 plat/arm/common/arm_nor_psci_mem_protect.c \ 299 ${FVP_CPU_LIBS} \ 300 ${FVP_GIC_SOURCES} \ 301 ${FVP_INTERCONNECT_SOURCES} \ 302 ${FVP_SECURITY_SOURCES} 303 304# Support for fconf in BL31 305# Added separately from the above list for better readability 306ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 307BL31_SOURCES += lib/fconf/fconf.c \ 308 lib/fconf/fconf_dyn_cfg_getter.c \ 309 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 310 311BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 312 313ifeq (${SEC_INT_DESC_IN_FCONF},1) 314BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 315endif 316 317endif 318 319ifeq (${USE_SP804_TIMER},1) 320BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 321else 322BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 323endif 324 325# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 326ifdef UNIX_MK 327FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 328FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 329 ${PLAT}_fw_config.dts \ 330 ${PLAT}_tb_fw_config.dts \ 331 ${PLAT}_soc_fw_config.dts \ 332 ${PLAT}_nt_fw_config.dts \ 333 ) 334 335FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 336FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 337FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 338FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 339 340ifeq (${SPD},tspd) 341FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 342FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 343 344# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 345$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 346endif 347 348ifeq (${SPD},spmd) 349 350ifeq ($(ARM_SPMC_MANIFEST_DTS),) 351ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 352endif 353 354FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 355FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 356 357# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 358$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 359endif 360 361# Add the FW_CONFIG to FIP and specify the same to certtool 362$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 363# Add the TB_FW_CONFIG to FIP and specify the same to certtool 364$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 365# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 366$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 367# Add the NT_FW_CONFIG to FIP and specify the same to certtool 368$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 369 370FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 371$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 372 373# Add the HW_CONFIG to FIP and specify the same to certtool 374$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 375endif 376 377# Enable dynamic mitigation support by default 378DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 379 380ifneq (${ENABLE_FEAT_AMU},0) 381BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 382 lib/cpus/aarch64/cpuamu_helpers.S 383 384ifeq (${HW_ASSISTED_COHERENCY}, 1) 385BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 386 lib/cpus/aarch64/neoverse_n1_pubsub.c 387endif 388endif 389 390ifeq (${RAS_EXTENSION},1) 391BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 392endif 393 394ifneq (${ENABLE_STACK_PROTECTOR},0) 395PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 396endif 397 398ifeq (${ARCH},aarch32) 399 NEED_BL32 := yes 400endif 401 402# Enable the dynamic translation tables library. 403ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 404 ifeq (${ARCH},aarch32) 405 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 406 else # AArch64 407 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 408 endif 409endif 410 411ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 412 ifeq (${ARCH},aarch32) 413 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 414 else # AArch64 415 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 416 ifeq (${SPD},tspd) 417 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 418 endif 419 endif 420endif 421 422ifeq (${USE_DEBUGFS},1) 423 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 424endif 425 426# Add support for platform supplied linker script for BL31 build 427$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 428 429ifneq (${RESET_TO_BL2}, 0) 430 override BL1_SOURCES = 431endif 432 433# RSS is not supported on FVP right now. Thus, we use the mocked version 434# of the provided PSA APIs. They return with success and hard-coded token/key. 435PLAT_RSS_NOT_SUPPORTED := 1 436 437# Include Measured Boot makefile before any Crypto library makefile. 438# Crypto library makefile may need default definitions of Measured Boot build 439# flags present in Measured Boot makefile. 440ifeq (${MEASURED_BOOT},1) 441 RSS_MEASURED_BOOT_MK := drivers/measured_boot/rss/rss_measured_boot.mk 442 $(info Including ${RSS_MEASURED_BOOT_MK}) 443 include ${RSS_MEASURED_BOOT_MK} 444 445 ifneq (${MBOOT_RSS_HASH_ALG}, sha256) 446 $(eval $(call add_define,TF_MBEDTLS_MBOOT_USE_SHA512)) 447 endif 448 449 BL1_SOURCES += ${MEASURED_BOOT_SOURCES} 450 BL2_SOURCES += ${MEASURED_BOOT_SOURCES} 451endif 452 453include plat/arm/board/common/board_common.mk 454include plat/arm/common/arm_common.mk 455 456ifeq (${MEASURED_BOOT},1) 457BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 458 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 459 lib/psa/measured_boot.c 460 461BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 462 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 463 lib/psa/measured_boot.c 464 465# Even though RSS is not supported on FVP (see above), we support overriding 466# PLAT_RSS_NOT_SUPPORTED from the command line, just for the purpose of building 467# the code to detect any build regressions. The resulting firmware will not be 468# functional. 469ifneq (${PLAT_RSS_NOT_SUPPORTED},1) 470 $(warning "RSS is not supported on FVP. The firmware will not be functional.") 471 include drivers/arm/rss/rss_comms.mk 472 BL1_SOURCES += ${RSS_COMMS_SOURCES} 473 BL2_SOURCES += ${RSS_COMMS_SOURCES} 474 BL31_SOURCES += ${RSS_COMMS_SOURCES} 475 476 BL1_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 477 BL2_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 478 BL31_CFLAGS += -DPLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0 479endif 480 481endif 482 483ifeq (${DRTM_SUPPORT}, 1) 484BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 485 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 486 plat/arm/board/fvp/fvp_drtm_err.c \ 487 plat/arm/board/fvp/fvp_drtm_measurement.c \ 488 plat/arm/board/fvp/fvp_drtm_stub.c \ 489 plat/arm/common/arm_dyn_cfg.c \ 490 plat/arm/board/fvp/fvp_err.c 491endif 492 493ifeq (${TRUSTED_BOARD_BOOT}, 1) 494BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 495BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 496 497# FVP being a development platform, enable capability to disable Authentication 498# dynamically if TRUSTED_BOARD_BOOT is set. 499DYN_DISABLE_AUTH := 1 500endif 501 502ifeq (${SPMC_AT_EL3}, 1) 503PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 504endif 505 506PSCI_OS_INIT_MODE := 1 507 508ifeq (${SPD},spmd) 509BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 510endif 511 512# Test specific macros, keep them at bottom of this file 513$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 514ifeq (${PLATFORM_TEST_EA_FFH}, 1) 515 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 516 $(error "PLATFORM_TEST_EA_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 517 endif 518BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 519endif 520 521$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 522ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 523 ifeq (${RAS_EXTENSION}, 0) 524 $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1") 525 endif 526endif 527