1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_MBOX_H 8 #define SOCFPGA_MBOX_H 9 10 #include <lib/utils_def.h> 11 12 13 #define MBOX_OFFSET 0xffa30000 14 15 #define MBOX_ATF_CLIENT_ID 0x1U 16 #define MBOX_MAX_JOB_ID 0xFU 17 #define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U) 18 #define MBOX_JOB_ID MBOX_MAX_JOB_ID 19 20 21 /* Mailbox Shared Memory Register Map */ 22 #define MBOX_CIN 0x00 23 #define MBOX_ROUT 0x04 24 #define MBOX_URG 0x08 25 #define MBOX_INT 0x0C 26 #define MBOX_COUT 0x20 27 #define MBOX_RIN 0x24 28 #define MBOX_STATUS 0x2C 29 #define MBOX_CMD_BUFFER 0x40 30 #define MBOX_RESP_BUFFER 0xC0 31 32 /* Mailbox SDM doorbell */ 33 #define MBOX_DOORBELL_TO_SDM 0x400 34 #define MBOX_DOORBELL_FROM_SDM 0x480 35 36 37 /* Mailbox commands */ 38 39 #define MBOX_CMD_NOOP 0x00 40 #define MBOX_CMD_SYNC 0x01 41 #define MBOX_CMD_RESTART 0x02 42 #define MBOX_CMD_CANCEL 0x03 43 #define MBOX_CMD_VAB_SRC_CERT 0x0B 44 #define MBOX_CMD_GET_IDCODE 0x10 45 #define MBOX_CMD_REBOOT_HPS 0x47 46 47 /* Reconfiguration Commands */ 48 #define MBOX_CONFIG_STATUS 0x04 49 #define MBOX_RECONFIG 0x06 50 #define MBOX_RECONFIG_DATA 0x08 51 #define MBOX_RECONFIG_STATUS 0x09 52 53 /* QSPI Commands */ 54 #define MBOX_CMD_QSPI_OPEN 0x32 55 #define MBOX_CMD_QSPI_CLOSE 0x33 56 #define MBOX_CMD_QSPI_SET_CS 0x34 57 #define MBOX_CMD_QSPI_DIRECT 0x3B 58 59 /* RSU Commands */ 60 #define MBOX_GET_SUBPARTITION_TABLE 0x5A 61 #define MBOX_RSU_STATUS 0x5B 62 #define MBOX_RSU_UPDATE 0x5C 63 #define MBOX_HPS_STAGE_NOTIFY 0x5D 64 65 /* FCS Command */ 66 #define MBOX_FCS_GET_PROVISION 0x7B 67 #define MBOX_FCS_ENCRYPT_REQ 0x7E 68 #define MBOX_FCS_DECRYPT_REQ 0x7F 69 #define MBOX_FCS_RANDOM_GEN 0x80 70 71 /* Mailbox Definitions */ 72 73 #define CMD_DIRECT 0 74 #define CMD_INDIRECT 1 75 #define CMD_CASUAL 0 76 #define CMD_URGENT 1 77 78 #define MBOX_WORD_BYTE 4U 79 #define MBOX_RESP_BUFFER_SIZE 16 80 #define MBOX_CMD_BUFFER_SIZE 32 81 82 /* Execution states for HPS_STAGE_NOTIFY */ 83 #define HPS_EXECUTION_STATE_FSBL 0 84 #define HPS_EXECUTION_STATE_SSBL 1 85 #define HPS_EXECUTION_STATE_OS 2 86 87 /* Status Response */ 88 #define MBOX_RET_OK 0 89 #define MBOX_RET_ERROR -1 90 #define MBOX_NO_RESPONSE -2 91 #define MBOX_WRONG_ID -3 92 #define MBOX_BUFFER_FULL -4 93 #define MBOX_TIMEOUT -2047 94 95 /* Reconfig Status Response */ 96 #define RECONFIG_STATUS_STATE 0 97 #define RECONFIG_STATUS_PIN_STATUS 2 98 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 99 #define PIN_STATUS_NSTATUS (U(1) << 31) 100 #define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) 101 #define SOFTFUNC_STATUS_INIT_DONE (1 << 1) 102 #define SOFTFUNC_STATUS_CONF_DONE (1 << 0) 103 #define MBOX_CFGSTAT_STATE_IDLE 0x00000000 104 #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 105 #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 106 #define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 107 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 108 #define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 109 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 110 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 111 #define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 112 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 113 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 114 115 116 /* Mailbox Macros */ 117 118 #define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \ 119 + MBOX_WORD_BYTE * (ptr)) 120 121 /* Mailbox interrupt flags and masks */ 122 #define MBOX_INT_FLAG_COE 0x1 123 #define MBOX_INT_FLAG_RIE 0x2 124 #define MBOX_INT_FLAG_UAE 0x100 125 #define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) 126 #define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8))) 127 128 /* Mailbox response and status */ 129 #define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff) 130 #define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) 131 #define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) 132 #define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) 133 #define MBOX_STATUS_UA_MASK (1<<8) 134 135 /* Mailbox command and response */ 136 #define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) 137 #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) 138 #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) 139 #define MBOX_INDIRECT(val) ((val) << 11) 140 #define MBOX_CMD_MASK(header) ((header) & 0x7ff) 141 142 /* RSU Macros */ 143 #define RSU_VERSION_ACMF BIT(8) 144 #define RSU_VERSION_ACMF_MASK 0xff00 145 146 147 /* Mailbox Function Definitions */ 148 149 void mailbox_set_int(uint32_t interrupt_input); 150 int mailbox_init(void); 151 void mailbox_set_qspi_close(void); 152 void mailbox_hps_qspi_enable(void); 153 154 int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args, 155 unsigned int len, uint32_t urgent, uint32_t *response, 156 unsigned int *resp_len); 157 int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args, 158 unsigned int len, unsigned int indirect); 159 int mailbox_read_response(uint32_t *job_id, uint32_t *response, 160 unsigned int *resp_len); 161 int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf, 162 unsigned int *resp_len); 163 164 void mailbox_reset_cold(void); 165 void mailbox_clear_response(void); 166 167 int intel_mailbox_get_config_status(uint32_t cmd, bool init_done); 168 int intel_mailbox_is_fpga_not_ready(void); 169 170 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len); 171 int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len); 172 int mailbox_rsu_update(uint32_t *flash_offset); 173 int mailbox_hps_stage_notify(uint32_t execution_stage); 174 175 #endif /* SOCFPGA_MBOX_H */ 176