1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp1-clksrc.h> 8#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" 9 10/ { 11 memory@c0000000 { 12 device_type = "memory"; 13 reg = <0xc0000000 0x20000000>; 14 }; 15 16 vin: vin { 17 compatible = "regulator-fixed"; 18 regulator-name = "vin"; 19 regulator-min-microvolt = <5000000>; 20 regulator-max-microvolt = <5000000>; 21 regulator-always-on; 22 }; 23}; 24 25&bsec { 26 board_id: board_id@ec { 27 reg = <0xec 0x4>; 28 st,non-secure-otp; 29 }; 30}; 31 32&clk_hse { 33 st,digbypass; 34}; 35 36&cpu0{ 37 cpu-supply = <&vddcore>; 38}; 39 40&cpu1{ 41 cpu-supply = <&vddcore>; 42}; 43 44&hash1 { 45 status = "okay"; 46}; 47 48&i2c4 { 49 pinctrl-names = "default"; 50 pinctrl-0 = <&i2c4_pins_a>; 51 i2c-scl-rising-time-ns = <185>; 52 i2c-scl-falling-time-ns = <20>; 53 clock-frequency = <400000>; 54 status = "okay"; 55 56 pmic: stpmic@33 { 57 compatible = "st,stpmic1"; 58 reg = <0x33>; 59 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 60 interrupt-controller; 61 #interrupt-cells = <2>; 62 status = "okay"; 63 64 regulators { 65 compatible = "st,stpmic1-regulators"; 66 buck1-supply = <&vin>; 67 buck2-supply = <&vin>; 68 buck3-supply = <&vin>; 69 buck4-supply = <&vin>; 70 ldo1-supply = <&v3v3>; 71 ldo2-supply = <&vin>; 72 ldo3-supply = <&vdd_ddr>; 73 ldo4-supply = <&vin>; 74 ldo5-supply = <&vin>; 75 ldo6-supply = <&v3v3>; 76 vref_ddr-supply = <&vin>; 77 boost-supply = <&vin>; 78 pwr_sw1-supply = <&bst_out>; 79 pwr_sw2-supply = <&bst_out>; 80 81 vddcore: buck1 { 82 regulator-name = "vddcore"; 83 regulator-min-microvolt = <1200000>; 84 regulator-max-microvolt = <1350000>; 85 regulator-always-on; 86 regulator-initial-mode = <0>; 87 regulator-over-current-protection; 88 }; 89 90 vdd_ddr: buck2 { 91 regulator-name = "vdd_ddr"; 92 regulator-min-microvolt = <1350000>; 93 regulator-max-microvolt = <1350000>; 94 regulator-always-on; 95 regulator-initial-mode = <0>; 96 regulator-over-current-protection; 97 }; 98 99 vdd: buck3 { 100 regulator-name = "vdd"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 regulator-always-on; 104 st,mask-reset; 105 regulator-initial-mode = <0>; 106 regulator-over-current-protection; 107 }; 108 109 v3v3: buck4 { 110 regulator-name = "v3v3"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 regulator-always-on; 114 regulator-over-current-protection; 115 regulator-initial-mode = <0>; 116 }; 117 118 v1v8_audio: ldo1 { 119 regulator-name = "v1v8_audio"; 120 regulator-min-microvolt = <1800000>; 121 regulator-max-microvolt = <1800000>; 122 regulator-always-on; 123 }; 124 125 v3v3_hdmi: ldo2 { 126 regulator-name = "v3v3_hdmi"; 127 regulator-min-microvolt = <3300000>; 128 regulator-max-microvolt = <3300000>; 129 regulator-always-on; 130 }; 131 132 vtt_ddr: ldo3 { 133 regulator-name = "vtt_ddr"; 134 regulator-always-on; 135 regulator-over-current-protection; 136 st,regulator-sink-source; 137 }; 138 139 vdd_usb: ldo4 { 140 regulator-name = "vdd_usb"; 141 regulator-min-microvolt = <3300000>; 142 regulator-max-microvolt = <3300000>; 143 }; 144 145 vdda: ldo5 { 146 regulator-name = "vdda"; 147 regulator-min-microvolt = <2900000>; 148 regulator-max-microvolt = <2900000>; 149 regulator-boot-on; 150 }; 151 152 v1v2_hdmi: ldo6 { 153 regulator-name = "v1v2_hdmi"; 154 regulator-min-microvolt = <1200000>; 155 regulator-max-microvolt = <1200000>; 156 regulator-always-on; 157 }; 158 159 vref_ddr: vref_ddr { 160 regulator-name = "vref_ddr"; 161 regulator-always-on; 162 }; 163 164 bst_out: boost { 165 regulator-name = "bst_out"; 166 }; 167 168 vbus_otg: pwr_sw1 { 169 regulator-name = "vbus_otg"; 170 }; 171 172 vbus_sw: pwr_sw2 { 173 regulator-name = "vbus_sw"; 174 regulator-active-discharge = <1>; 175 }; 176 }; 177 }; 178}; 179 180&iwdg2 { 181 timeout-sec = <32>; 182 status = "okay"; 183 secure-status = "okay"; 184}; 185 186&nvmem_layout { 187 nvmem-cells = <&cfg0_otp>, 188 <&part_number_otp>, 189 <&monotonic_otp>, 190 <&nand_otp>, 191 <&uid_otp>, 192 <&package_otp>, 193 <&hw2_otp>, 194 <&board_id>; 195 196 nvmem-cell-names = "cfg0_otp", 197 "part_number_otp", 198 "monotonic_otp", 199 "nand_otp", 200 "uid_otp", 201 "package_otp", 202 "hw2_otp", 203 "board_id"; 204}; 205 206&pwr_regulators { 207 vdd-supply = <&vdd>; 208 vdd_3v3_usbfs-supply = <&vdd_usb>; 209}; 210 211&rcc { 212 secure-status = "disabled"; 213 st,clksrc = < 214 CLK_MPU_PLL1P 215 CLK_AXI_PLL2P 216 CLK_MCU_PLL3P 217 CLK_PLL12_HSE 218 CLK_PLL3_HSE 219 CLK_PLL4_HSE 220 CLK_RTC_LSE 221 CLK_MCO1_DISABLED 222 CLK_MCO2_DISABLED 223 >; 224 225 st,clkdiv = < 226 1 /*MPU*/ 227 0 /*AXI*/ 228 0 /*MCU*/ 229 1 /*APB1*/ 230 1 /*APB2*/ 231 1 /*APB3*/ 232 1 /*APB4*/ 233 2 /*APB5*/ 234 23 /*RTC*/ 235 0 /*MCO1*/ 236 0 /*MCO2*/ 237 >; 238 239 st,pkcs = < 240 CLK_CKPER_HSE 241 CLK_FMC_ACLK 242 CLK_QSPI_ACLK 243 CLK_ETH_PLL4P 244 CLK_SDMMC12_PLL4P 245 CLK_DSI_DSIPLL 246 CLK_STGEN_HSE 247 CLK_USBPHY_HSE 248 CLK_SPI2S1_PLL3Q 249 CLK_SPI2S23_PLL3Q 250 CLK_SPI45_HSI 251 CLK_SPI6_HSI 252 CLK_I2C46_HSI 253 CLK_SDMMC3_PLL4P 254 CLK_USBO_USBPHY 255 CLK_ADC_CKPER 256 CLK_CEC_LSE 257 CLK_I2C12_HSI 258 CLK_I2C35_HSI 259 CLK_UART1_HSI 260 CLK_UART24_HSI 261 CLK_UART35_HSI 262 CLK_UART6_HSI 263 CLK_UART78_HSI 264 CLK_SPDIF_PLL4P 265 CLK_FDCAN_PLL4R 266 CLK_SAI1_PLL3Q 267 CLK_SAI2_PLL3Q 268 CLK_SAI3_PLL3Q 269 CLK_SAI4_PLL3Q 270 CLK_RNG1_LSI 271 CLK_RNG2_LSI 272 CLK_LPTIM1_PCLK1 273 CLK_LPTIM23_PCLK3 274 CLK_LPTIM45_LSE 275 >; 276 277 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 278 pll1: st,pll@0 { 279 compatible = "st,stm32mp1-pll"; 280 reg = <0>; 281 cfg = < 2 80 0 0 0 PQR(1,0,0) >; 282 frac = < 0x800 >; 283 }; 284 285 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 286 pll2: st,pll@1 { 287 compatible = "st,stm32mp1-pll"; 288 reg = <1>; 289 cfg = <2 65 1 0 0 PQR(1,1,1)>; 290 frac = <0x1400>; 291 }; 292 293 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 294 pll3: st,pll@2 { 295 compatible = "st,stm32mp1-pll"; 296 reg = <2>; 297 cfg = <1 33 1 16 36 PQR(1,1,1)>; 298 frac = <0x1a04>; 299 }; 300 301 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 302 pll4: st,pll@3 { 303 compatible = "st,stm32mp1-pll"; 304 reg = <3>; 305 cfg = <3 98 5 7 7 PQR(1,1,1)>; 306 }; 307}; 308 309&rng1 { 310 status = "okay"; 311}; 312 313&rtc { 314 status = "okay"; 315}; 316 317&sdmmc1 { 318 pinctrl-names = "default"; 319 pinctrl-0 = <&sdmmc1_b4_pins_a>; 320 disable-wp; 321 st,neg-edge; 322 bus-width = <4>; 323 vmmc-supply = <&v3v3>; 324 status = "okay"; 325}; 326 327&timers15 { 328 secure-status = "okay"; 329}; 330 331&uart4 { 332 pinctrl-names = "default"; 333 pinctrl-0 = <&uart4_pins_a>; 334 status = "okay"; 335}; 336 337&uart7 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&uart7_pins_c>; 340 status = "disabled"; 341}; 342 343&usart3 { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&usart3_pins_c>; 346 uart-has-rtscts; 347 status = "disabled"; 348}; 349 350&usbotg_hs { 351 phys = <&usbphyc_port1 0>; 352 phy-names = "usb2-phy"; 353 usb-role-switch; 354 status = "okay"; 355}; 356 357&usbphyc { 358 status = "okay"; 359}; 360 361&usbphyc_port0 { 362 phy-supply = <&vdd_usb>; 363}; 364 365&usbphyc_port1 { 366 phy-supply = <&vdd_usb>; 367}; 368