1/* 2 * Copyright (c) 2019-2021, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19 20/* -------------------------------------------------- 21 * Errata Workaround for A78 Erratum 1688305. 22 * This applies to revision r0p0 and r1p0 of A78. 23 * Inputs: 24 * x0: variant[4:7] and revision[0:3] of current cpu. 25 * Shall clobber: x0-x17 26 * -------------------------------------------------- 27 */ 28func errata_a78_1688305_wa 29 /* Compare x0 against revision r1p0 */ 30 mov x17, x30 31 bl check_errata_1688305 32 cbz x0, 1f 33 mrs x1, CORTEX_A78_ACTLR2_EL1 34 orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1 35 msr CORTEX_A78_ACTLR2_EL1, x1 36 isb 371: 38 ret x17 39endfunc errata_a78_1688305_wa 40 41func check_errata_1688305 42 /* Applies to r0p0 and r1p0 */ 43 mov x1, #0x10 44 b cpu_rev_var_ls 45endfunc check_errata_1688305 46 47/* -------------------------------------------------- 48 * Errata Workaround for Cortex A78 Errata #1941498. 49 * This applies to revisions r0p0, r1p0, and r1p1. 50 * x0: variant[4:7] and revision[0:3] of current cpu. 51 * Shall clobber: x0-x17 52 * -------------------------------------------------- 53 */ 54func errata_a78_1941498_wa 55 /* Compare x0 against revision <= r1p1 */ 56 mov x17, x30 57 bl check_errata_1941498 58 cbz x0, 1f 59 60 /* Set bit 8 in ECTLR_EL1 */ 61 mrs x1, CORTEX_A78_CPUECTLR_EL1 62 orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8 63 msr CORTEX_A78_CPUECTLR_EL1, x1 64 isb 651: 66 ret x17 67endfunc errata_a78_1941498_wa 68 69func check_errata_1941498 70 /* Check for revision <= r1p1, might need to be updated later. */ 71 mov x1, #0x11 72 b cpu_rev_var_ls 73endfunc check_errata_1941498 74 75/* -------------------------------------------------- 76 * Errata Workaround for A78 Erratum 1951500. 77 * This applies to revisions r1p0 and r1p1 of A78. 78 * The issue also exists in r0p0 but there is no fix 79 * in that revision. 80 * Inputs: 81 * x0: variant[4:7] and revision[0:3] of current cpu. 82 * Shall clobber: x0-x17 83 * -------------------------------------------------- 84 */ 85func errata_a78_1951500_wa 86 /* Compare x0 against revisions r1p0 - r1p1 */ 87 mov x17, x30 88 bl check_errata_1951500 89 cbz x0, 1f 90 91 msr S3_6_c15_c8_0, xzr 92 ldr x0, =0x10E3900002 93 msr S3_6_c15_c8_2, x0 94 ldr x0, =0x10FFF00083 95 msr S3_6_c15_c8_3, x0 96 ldr x0, =0x2001003FF 97 msr S3_6_c15_c8_1, x0 98 99 mov x0, #1 100 msr S3_6_c15_c8_0, x0 101 ldr x0, =0x10E3800082 102 msr S3_6_c15_c8_2, x0 103 ldr x0, =0x10FFF00083 104 msr S3_6_c15_c8_3, x0 105 ldr x0, =0x2001003FF 106 msr S3_6_c15_c8_1, x0 107 108 mov x0, #2 109 msr S3_6_c15_c8_0, x0 110 ldr x0, =0x10E3800200 111 msr S3_6_c15_c8_2, x0 112 ldr x0, =0x10FFF003E0 113 msr S3_6_c15_c8_3, x0 114 ldr x0, =0x2001003FF 115 msr S3_6_c15_c8_1, x0 116 117 isb 1181: 119 ret x17 120endfunc errata_a78_1951500_wa 121 122func check_errata_1951500 123 /* Applies to revisions r1p0 and r1p1. */ 124 mov x1, #CPU_REV(1, 0) 125 mov x2, #CPU_REV(1, 1) 126 b cpu_rev_var_range 127endfunc check_errata_1951500 128 129/* -------------------------------------------------- 130 * Errata Workaround for Cortex A78 Errata #1821534. 131 * This applies to revisions r0p0 and r1p0. 132 * x0: variant[4:7] and revision[0:3] of current cpu. 133 * Shall clobber: x0-x17 134 * -------------------------------------------------- 135 */ 136func errata_a78_1821534_wa 137 /* Check revision. */ 138 mov x17, x30 139 bl check_errata_1821534 140 cbz x0, 1f 141 142 /* Set bit 2 in ACTLR2_EL1 */ 143 mrs x1, CORTEX_A78_ACTLR2_EL1 144 orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2 145 msr CORTEX_A78_ACTLR2_EL1, x1 146 isb 1471: 148 ret x17 149endfunc errata_a78_1821534_wa 150 151func check_errata_1821534 152 /* Applies to r0p0 and r1p0 */ 153 mov x1, #0x10 154 b cpu_rev_var_ls 155endfunc check_errata_1821534 156 157/* -------------------------------------------------- 158 * Errata Workaround for Cortex A78 Errata 1952683. 159 * This applies to revision r0p0. 160 * x0: variant[4:7] and revision[0:3] of current cpu. 161 * Shall clobber: x0-x17 162 * -------------------------------------------------- 163 */ 164func errata_a78_1952683_wa 165 /* Check revision. */ 166 mov x17, x30 167 bl check_errata_1952683 168 cbz x0, 1f 169 170 ldr x0,=0x5 171 msr S3_6_c15_c8_0,x0 172 ldr x0,=0xEEE10A10 173 msr S3_6_c15_c8_2,x0 174 ldr x0,=0xFFEF0FFF 175 msr S3_6_c15_c8_3,x0 176 ldr x0,=0x0010F000 177 msr S3_6_c15_c8_4,x0 178 ldr x0,=0x0010F000 179 msr S3_6_c15_c8_5,x0 180 ldr x0,=0x40000080023ff 181 msr S3_6_c15_c8_1,x0 182 ldr x0,=0x6 183 msr S3_6_c15_c8_0,x0 184 ldr x0,=0xEE640F34 185 msr S3_6_c15_c8_2,x0 186 ldr x0,=0xFFEF0FFF 187 msr S3_6_c15_c8_3,x0 188 ldr x0,=0x40000080023ff 189 msr S3_6_c15_c8_1,x0 190 isb 1911: 192 ret x17 193endfunc errata_a78_1952683_wa 194 195func check_errata_1952683 196 /* Applies to r0p0 only */ 197 mov x1, #0x00 198 b cpu_rev_var_ls 199endfunc check_errata_1952683 200 201/* -------------------------------------------------- 202 * Errata Workaround for Cortex A78 Errata 2132060. 203 * This applies to revisions r0p0, r1p0, r1p1, and r1p2. 204 * It is still open. 205 * x0: variant[4:7] and revision[0:3] of current cpu. 206 * Shall clobber: x0-x1, x17 207 * -------------------------------------------------- 208 */ 209func errata_a78_2132060_wa 210 /* Check revision. */ 211 mov x17, x30 212 bl check_errata_2132060 213 cbz x0, 1f 214 215 /* Apply the workaround. */ 216 mrs x1, CORTEX_A78_CPUECTLR_EL1 217 mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV 218 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH 219 msr CORTEX_A78_CPUECTLR_EL1, x1 2201: 221 ret x17 222endfunc errata_a78_2132060_wa 223 224func check_errata_2132060 225 /* Applies to r0p0, r0p1, r1p1, and r1p2 */ 226 mov x1, #0x12 227 b cpu_rev_var_ls 228endfunc check_errata_2132060 229 230 /* ------------------------------------------------- 231 * The CPU Ops reset function for Cortex-A78 232 * ------------------------------------------------- 233 */ 234func cortex_a78_reset_func 235 mov x19, x30 236 bl cpu_get_rev_var 237 mov x18, x0 238 239#if ERRATA_A78_1688305 240 mov x0, x18 241 bl errata_a78_1688305_wa 242#endif 243 244#if ERRATA_A78_1941498 245 mov x0, x18 246 bl errata_a78_1941498_wa 247#endif 248 249#if ERRATA_A78_1951500 250 mov x0, x18 251 bl errata_a78_1951500_wa 252#endif 253 254#if ERRATA_A78_1821534 255 mov x0, x18 256 bl errata_a78_1821534_wa 257#endif 258 259#if ERRATA_A78_1952683 260 mov x0, x18 261 bl errata_a78_1952683_wa 262#endif 263 264#if ERRATA_A78_2132060 265 mov x0, x18 266 bl errata_a78_2132060_wa 267#endif 268 269#if ENABLE_AMU 270 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 271 mrs x0, actlr_el3 272 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 273 msr actlr_el3, x0 274 275 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 276 mrs x0, actlr_el2 277 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT 278 msr actlr_el2, x0 279 280 /* Enable group0 counters */ 281 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 282 msr CPUAMCNTENSET0_EL0, x0 283 284 /* Enable group1 counters */ 285 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 286 msr CPUAMCNTENSET1_EL0, x0 287#endif 288 289 isb 290 ret x19 291endfunc cortex_a78_reset_func 292 293 /* --------------------------------------------- 294 * HW will do the cache maintenance while powering down 295 * --------------------------------------------- 296 */ 297func cortex_a78_core_pwr_dwn 298 /* --------------------------------------------- 299 * Enable CPU power down bit in power control register 300 * --------------------------------------------- 301 */ 302 mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 303 orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 304 msr CORTEX_A78_CPUPWRCTLR_EL1, x0 305 isb 306 ret 307endfunc cortex_a78_core_pwr_dwn 308 309 /* 310 * Errata printing function for cortex_a78. Must follow AAPCS. 311 */ 312#if REPORT_ERRATA 313func cortex_a78_errata_report 314 stp x8, x30, [sp, #-16]! 315 316 bl cpu_get_rev_var 317 mov x8, x0 318 319 /* 320 * Report all errata. The revision-variant information is passed to 321 * checking functions of each errata. 322 */ 323 report_errata ERRATA_A78_1688305, cortex_a78, 1688305 324 report_errata ERRATA_A78_1941498, cortex_a78, 1941498 325 report_errata ERRATA_A78_1951500, cortex_a78, 1951500 326 report_errata ERRATA_A78_1821534, cortex_a78, 1821534 327 report_errata ERRATA_A78_1952683, cortex_a78, 1952683 328 report_errata ERRATA_A78_2132060, cortex_a78, 2132060 329 330 ldp x8, x30, [sp], #16 331 ret 332endfunc cortex_a78_errata_report 333#endif 334 335 /* --------------------------------------------- 336 * This function provides cortex_a78 specific 337 * register information for crash reporting. 338 * It needs to return with x6 pointing to 339 * a list of register names in ascii and 340 * x8 - x15 having values of registers to be 341 * reported. 342 * --------------------------------------------- 343 */ 344.section .rodata.cortex_a78_regs, "aS" 345cortex_a78_regs: /* The ascii list of register names to be reported */ 346 .asciz "cpuectlr_el1", "" 347 348func cortex_a78_cpu_reg_dump 349 adr x6, cortex_a78_regs 350 mrs x8, CORTEX_A78_CPUECTLR_EL1 351 ret 352endfunc cortex_a78_cpu_reg_dump 353 354declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 355 cortex_a78_reset_func, \ 356 cortex_a78_core_pwr_dwn 357