1 /* 2 * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <plat_arm.h> 10 #include <plat_private.h> 11 #include <bl31/bl31.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/arm/dcc.h> 15 #include <drivers/arm/pl011.h> 16 #include <drivers/console.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables.h> 19 #include <plat/common/platform.h> 20 #include <versal_def.h> 21 #include <plat_private.h> 22 #include <plat_startup.h> 23 24 static entry_point_info_t bl32_image_ep_info; 25 static entry_point_info_t bl33_image_ep_info; 26 27 /* 28 * Return a pointer to the 'entry_point_info' structure of the next image for 29 * the security state specified. BL33 corresponds to the non-secure image type 30 * while BL32 corresponds to the secure image type. A NULL pointer is returned 31 * if the image does not exist. 32 */ 33 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 34 { 35 assert(sec_state_is_valid(type)); 36 37 if (type == NON_SECURE) { 38 return &bl33_image_ep_info; 39 } 40 41 return &bl32_image_ep_info; 42 } 43 44 /* 45 * Set the build time defaults,if we can't find any config data. 46 */ 47 static inline void bl31_set_default_config(void) 48 { 49 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 50 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); 51 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); 52 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 53 DISABLE_ALL_EXCEPTIONS); 54 } 55 56 /* 57 * Perform any BL31 specific platform actions. Here is an opportunity to copy 58 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 59 * are lost (potentially). This needs to be done before the MMU is initialized 60 * so that the memory layout can be used while creating page tables. 61 */ 62 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 63 u_register_t arg2, u_register_t arg3) 64 { 65 uint64_t atf_handoff_addr; 66 67 if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) { 68 static console_t versal_runtime_console; 69 /* Initialize the console to provide early debug support */ 70 int rc = console_pl011_register((unsigned long)VERSAL_UART_BASE, 71 (unsigned int)VERSAL_UART_CLOCK, 72 (unsigned int)VERSAL_UART_BAUDRATE, 73 &versal_runtime_console); 74 if (rc == 0) { 75 panic(); 76 } 77 78 console_set_scope(&versal_runtime_console, (unsigned int)(CONSOLE_FLAG_BOOT | 79 CONSOLE_FLAG_RUNTIME)); 80 } else if (VERSAL_CONSOLE_IS(dcc)) { 81 /* Initialize the dcc console for debug */ 82 int rc = console_dcc_register(); 83 if (rc == 0) { 84 panic(); 85 } 86 } else { 87 NOTICE("BL31: Did not register for any console.\n"); 88 } 89 90 /* Initialize the platform config for future decision making */ 91 versal_config_setup(); 92 /* There are no parameters from BL2 if BL31 is a reset vector */ 93 assert(arg0 == 0U); 94 assert(arg1 == 0U); 95 96 /* 97 * Do initial security configuration to allow DRAM/device access. On 98 * Base VERSAL only DRAM security is programmable (via TrustZone), but 99 * other platforms might have more programmable security devices 100 * present. 101 */ 102 103 /* Populate common information for BL32 and BL33 */ 104 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 105 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 106 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 107 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 108 109 atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); 110 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, 111 &bl33_image_ep_info, 112 atf_handoff_addr); 113 if (ret == FSBL_HANDOFF_NO_STRUCT || ret == FSBL_HANDOFF_INVAL_STRUCT) { 114 bl31_set_default_config(); 115 } else if (ret == FSBL_HANDOFF_TOO_MANY_PARTS) { 116 ERROR("BL31: Error too many partitions %u\n", ret); 117 } else if (ret != FSBL_HANDOFF_SUCCESS) { 118 panic(); 119 } else { 120 INFO("BL31: fsbl-atf handover success %u\n", ret); 121 } 122 123 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 124 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 125 } 126 127 static interrupt_type_handler_t type_el3_interrupt_handler; 128 129 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 130 { 131 /* Validate 'handler'*/ 132 if (handler == NULL) { 133 return -EINVAL; 134 } 135 136 type_el3_interrupt_handler = handler; 137 138 return 0; 139 } 140 141 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 142 void *handle, void *cookie) 143 { 144 uint32_t intr_id; 145 interrupt_type_handler_t handler; 146 147 intr_id = plat_ic_get_pending_interrupt_id(); 148 /* Currently we support one interrupt */ 149 if (intr_id != PLAT_VERSAL_IPI_IRQ) { 150 WARN("Unexpected interrupt call: 0x%x\n", intr_id); 151 return 0; 152 } 153 154 handler = type_el3_interrupt_handler; 155 if (handler != NULL) { 156 return handler(intr_id, flags, handle, cookie); 157 } 158 159 return 0; 160 } 161 void bl31_platform_setup(void) 162 { 163 /* Initialize the gic cpu and distributor interfaces */ 164 plat_versal_gic_driver_init(); 165 plat_versal_gic_init(); 166 } 167 168 void bl31_plat_runtime_setup(void) 169 { 170 uint64_t flags = 0; 171 int32_t rc; 172 173 set_interrupt_rm_flag(flags, NON_SECURE); 174 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 175 rdo_el3_interrupt_handler, flags); 176 if (rc != 0) { 177 panic(); 178 } 179 } 180 181 /* 182 * Perform the very early platform specific architectural setup here. 183 */ 184 void bl31_plat_arch_setup(void) 185 { 186 plat_arm_interconnect_init(); 187 plat_arm_interconnect_enter_coherency(); 188 189 const mmap_region_t bl_regions[] = { 190 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 191 MT_MEMORY | MT_RW | MT_SECURE), 192 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 193 MT_CODE | MT_SECURE), 194 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 195 MT_RO_DATA | MT_SECURE), 196 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 197 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 198 MT_DEVICE | MT_RW | MT_SECURE), 199 {0} 200 }; 201 202 setup_page_tables(bl_regions, plat_versal_get_mmap()); 203 enable_mmu_el3(0); 204 } 205