1 /* 2 * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 21 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 22 U(FVP_MAX_PE_PER_CPU)) 23 24 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 25 PLATFORM_CORE_COUNT + U(1)) 26 27 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 28 29 /* 30 * Other platform porting definitions are provided by included headers 31 */ 32 33 /* 34 * Required ARM standard platform porting definitions 35 */ 36 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 37 38 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 39 40 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 41 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 42 43 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 44 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 45 46 #if ENABLE_RME 47 #define PLAT_ARM_RMM_BASE (RMM_BASE) 48 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 49 #endif 50 51 /* 52 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 53 * max size of BL32 image. 54 */ 55 #if defined(SPD_spmd) 56 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 57 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 58 #endif 59 60 /* virtual address used by dynamic mem_protect for chunk_base */ 61 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 62 63 /* No SCP in FVP */ 64 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 65 66 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 67 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 68 69 /* Range of kernel DTB load address */ 70 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 71 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 72 73 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 74 FVP_DTB_DRAM_MAP_START, \ 75 FVP_DTB_DRAM_MAP_SIZE, \ 76 MT_MEMORY | MT_RO | MT_NS) 77 /* 78 * Load address of BL33 for this platform port 79 */ 80 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 81 82 /* 83 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 84 * plat_arm_mmap array defined for each BL stage. 85 */ 86 #if defined(IMAGE_BL31) 87 # if SPM_MM 88 # define PLAT_ARM_MMAP_ENTRIES 10 89 # if ENABLE_RME 90 # define MAX_XLAT_TABLES 10 91 # else 92 # define MAX_XLAT_TABLES 9 93 # endif 94 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 95 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 96 # else 97 # define PLAT_ARM_MMAP_ENTRIES 9 98 # if USE_DEBUGFS 99 # if ENABLE_RME 100 # define MAX_XLAT_TABLES 9 101 # else 102 # define MAX_XLAT_TABLES 8 103 # endif 104 # else 105 # if ENABLE_RME 106 # define MAX_XLAT_TABLES 8 107 # else 108 # define MAX_XLAT_TABLES 7 109 # endif 110 # endif 111 # endif 112 #elif defined(IMAGE_BL32) 113 # define PLAT_ARM_MMAP_ENTRIES 9 114 # define MAX_XLAT_TABLES 6 115 #elif !USE_ROMLIB 116 # define PLAT_ARM_MMAP_ENTRIES 11 117 # define MAX_XLAT_TABLES 5 118 #else 119 # define PLAT_ARM_MMAP_ENTRIES 12 120 # define MAX_XLAT_TABLES 6 121 #endif 122 123 /* 124 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 125 * plus a little space for growth. 126 */ 127 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 128 129 /* 130 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 131 */ 132 133 #if USE_ROMLIB 134 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 135 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 136 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 137 #else 138 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 139 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 140 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 141 #endif 142 143 /* 144 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 145 * little space for growth. 146 */ 147 #if TRUSTED_BOARD_BOOT && COT_DESC_IN_DTB 148 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) 149 #elif CRYPTO_SUPPORT 150 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 151 #else 152 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) 153 #endif 154 155 #if RESET_TO_BL31 156 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 157 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 158 ARM_SHARED_RAM_SIZE - \ 159 ARM_L0_GPT_SIZE) 160 #else 161 /* 162 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 163 * calculated using the current BL31 PROGBITS debug size plus the sizes of 164 * BL2 and BL1-RW 165 */ 166 #define PLAT_ARM_MAX_BL31_SIZE (UL(0x3D000) - ARM_L0_GPT_SIZE) 167 #endif /* RESET_TO_BL31 */ 168 169 #ifndef __aarch64__ 170 #if RESET_TO_SP_MIN 171 /* Size of Trusted SRAM - the first 4KB of shared memory */ 172 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 173 ARM_SHARED_RAM_SIZE) 174 #else 175 /* 176 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 177 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 178 * BL2 and BL1-RW 179 */ 180 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 181 #endif /* RESET_TO_SP_MIN */ 182 #endif 183 184 /* 185 * Size of cacheable stacks 186 */ 187 #if defined(IMAGE_BL1) 188 # if CRYPTO_SUPPORT 189 # define PLATFORM_STACK_SIZE UL(0x1000) 190 # else 191 # define PLATFORM_STACK_SIZE UL(0x500) 192 # endif /* CRYPTO_SUPPORT */ 193 #elif defined(IMAGE_BL2) 194 # if CRYPTO_SUPPORT 195 # define PLATFORM_STACK_SIZE UL(0x1000) 196 # else 197 # define PLATFORM_STACK_SIZE UL(0x600) 198 # endif /* CRYPTO_SUPPORT */ 199 #elif defined(IMAGE_BL2U) 200 # define PLATFORM_STACK_SIZE UL(0x400) 201 #elif defined(IMAGE_BL31) 202 # define PLATFORM_STACK_SIZE UL(0x800) 203 #elif defined(IMAGE_BL32) 204 # define PLATFORM_STACK_SIZE UL(0x440) 205 #elif defined(IMAGE_RMM) 206 # define PLATFORM_STACK_SIZE UL(0x440) 207 #endif 208 209 #define MAX_IO_DEVICES 3 210 #define MAX_IO_HANDLES 4 211 212 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 213 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 214 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 215 216 #if ARM_GPT_SUPPORT 217 /* 218 * Offset of the FIP in the GPT image. BL1 component uses this option 219 * as it does not load the partition table to get the FIP base 220 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 221 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 222 */ 223 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 224 #endif /* ARM_GPT_SUPPORT */ 225 226 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 227 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 228 229 /* 230 * PL011 related constants 231 */ 232 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 233 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 234 235 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 236 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 237 238 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 239 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 240 241 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 242 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 243 244 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 245 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 246 247 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 248 249 /* CCI related constants */ 250 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 251 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 252 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 253 254 /* CCI-500/CCI-550 on Base platform */ 255 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 256 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 257 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 258 259 /* CCN related constants. Only CCN 502 is currently supported */ 260 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 261 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 262 263 /* System timer related constants */ 264 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 265 266 /* Mailbox base address */ 267 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 268 269 270 /* TrustZone controller related constants 271 * 272 * Currently only filters 0 and 2 are connected on Base FVP. 273 * Filter 0 : CPU clusters (no access to DRAM by default) 274 * Filter 1 : not connected 275 * Filter 2 : LCDs (access to VRAM allowed by default) 276 * Filter 3 : not connected 277 * Programming unconnected filters will have no effect at the 278 * moment. These filter could, however, be connected in future. 279 * So care should be taken not to configure the unused filters. 280 * 281 * Allow only non-secure access to all DRAM to supported devices. 282 * Give access to the CPUs and Virtio. Some devices 283 * would normally use the default ID so allow that too. 284 */ 285 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 286 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 287 288 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 289 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 290 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 291 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 292 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 293 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 294 295 /* 296 * GIC related constants to cater for both GICv2 and GICv3 instances of an 297 * FVP. They could be overridden at runtime in case the FVP implements the 298 * legacy VE memory map. 299 */ 300 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 301 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 302 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 303 304 /* 305 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 306 * terminology. On a GICv2 system or mode, the lists will be merged and treated 307 * as Group 0 interrupts. 308 */ 309 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 310 ARM_G1S_IRQ_PROPS(grp), \ 311 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 312 GIC_INTR_CFG_LEVEL), \ 313 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 314 GIC_INTR_CFG_LEVEL) 315 316 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 317 318 #if SDEI_IN_FCONF 319 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 320 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 321 #else 322 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 323 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 324 #endif 325 326 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 327 PLAT_SP_IMAGE_NS_BUF_SIZE) 328 329 #define PLAT_SP_PRI PLAT_RAS_PRI 330 331 /* 332 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 333 */ 334 #ifdef __aarch64__ 335 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 336 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 337 #else 338 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 339 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 340 #endif 341 342 /* 343 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 344 */ 345 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 346 347 #endif /* PLATFORM_DEF_H */ 348