1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gic_common.h> 14 15 #include "../common/gic_common_private.h" 16 #include "gicv3_private.h" 17 18 /****************************************************************************** 19 * This function marks the core as awake in the re-distributor and 20 * ensures that the interface is active. 21 *****************************************************************************/ 22 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 23 { 24 /* 25 * The WAKER_PS_BIT should be changed to 0 26 * only when WAKER_CA_BIT is 1. 27 */ 28 assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U); 29 30 /* Mark the connected core as awake */ 31 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 32 33 /* Wait till the WAKER_CA_BIT changes to 0 */ 34 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U) { 35 } 36 } 37 38 /****************************************************************************** 39 * This function marks the core as asleep in the re-distributor and ensures 40 * that the interface is quiescent. 41 *****************************************************************************/ 42 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 43 { 44 /* Mark the connected core as asleep */ 45 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 46 47 /* Wait till the WAKER_CA_BIT changes to 1 */ 48 while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U) { 49 } 50 } 51 52 /******************************************************************************* 53 * This function probes the Redistributor frames when the driver is initialised 54 * and saves their base addresses. These base addresses are used later to 55 * initialise each Redistributor interface. 56 ******************************************************************************/ 57 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 58 unsigned int rdistif_num, 59 uintptr_t gicr_base, 60 mpidr_hash_fn mpidr_to_core_pos) 61 { 62 u_register_t mpidr; 63 unsigned int proc_num; 64 uint64_t typer_val; 65 uintptr_t rdistif_base = gicr_base; 66 67 assert(rdistif_base_addrs != NULL); 68 69 /* 70 * Iterate over the Redistributor frames. Store the base address of each 71 * frame in the platform provided array. Use the "Processor Number" 72 * field to index into the array if the platform has not provided a hash 73 * function to convert an MPIDR (obtained from the "Affinity Value" 74 * field into a linear index. 75 */ 76 do { 77 typer_val = gicr_read_typer(rdistif_base); 78 if (mpidr_to_core_pos != NULL) { 79 mpidr = mpidr_from_gicr_typer(typer_val); 80 proc_num = mpidr_to_core_pos(mpidr); 81 } else { 82 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 83 TYPER_PROC_NUM_MASK; 84 } 85 86 if (proc_num < rdistif_num) { 87 rdistif_base_addrs[proc_num] = rdistif_base; 88 } 89 rdistif_base += gicv3_redist_size(typer_val); 90 } while ((typer_val & TYPER_LAST_BIT) == 0U); 91 } 92 93 /******************************************************************************* 94 * Helper function to get the maximum SPI INTID + 1. 95 ******************************************************************************/ 96 unsigned int gicv3_get_spi_limit(uintptr_t gicd_base) 97 { 98 unsigned int spi_limit; 99 unsigned int typer_reg = gicd_read_typer(gicd_base); 100 101 /* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */ 102 spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 103 104 /* Filter out special INTIDs 1020-1023 */ 105 if (spi_limit > (MAX_SPI_ID + 1U)) { 106 return MAX_SPI_ID + 1U; 107 } 108 109 return spi_limit; 110 } 111 112 #if GIC_EXT_INTID 113 /******************************************************************************* 114 * Helper function to get the maximum ESPI INTID + 1. 115 ******************************************************************************/ 116 unsigned int gicv3_get_espi_limit(uintptr_t gicd_base) 117 { 118 unsigned int typer_reg = gicd_read_typer(gicd_base); 119 120 /* Check if extended SPI range is implemented */ 121 if ((typer_reg & TYPER_ESPI) != 0U) { 122 /* 123 * (maximum ESPI INTID + 1) is equal to 124 * 32 * (GICD_TYPER.ESPI_range + 1) + 4096 125 */ 126 return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 127 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID; 128 } 129 130 return 0U; 131 } 132 #endif /* GIC_EXT_INTID */ 133 134 /******************************************************************************* 135 * Helper function to configure the default attributes of (E)SPIs. 136 ******************************************************************************/ 137 void gicv3_spis_config_defaults(uintptr_t gicd_base) 138 { 139 unsigned int i, num_ints; 140 #if GIC_EXT_INTID 141 unsigned int num_eints; 142 #endif 143 144 num_ints = gicv3_get_spi_limit(gicd_base); 145 INFO("Maximum SPI INTID supported: %u\n", num_ints - 1); 146 147 /* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */ 148 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { 149 gicd_write_igroupr(gicd_base, i, ~0U); 150 } 151 152 #if GIC_EXT_INTID 153 num_eints = gicv3_get_espi_limit(gicd_base); 154 if (num_eints != 0U) { 155 INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1); 156 157 for (i = MIN_ESPI_ID; i < num_eints; 158 i += (1U << IGROUPR_SHIFT)) { 159 gicd_write_igroupr(gicd_base, i, ~0U); 160 } 161 } else { 162 INFO("ESPI range is not implemented.\n"); 163 } 164 #endif 165 166 /* Setup the default (E)SPI priorities doing four at a time */ 167 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { 168 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 169 } 170 171 #if GIC_EXT_INTID 172 for (i = MIN_ESPI_ID; i < num_eints; 173 i += (1U << IPRIORITYR_SHIFT)) { 174 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 175 } 176 #endif 177 /* 178 * Treat all (E)SPIs as level triggered by default, write 16 at a time 179 */ 180 for (i = MIN_SPI_ID; i < num_ints; i += (1U << ICFGR_SHIFT)) { 181 gicd_write_icfgr(gicd_base, i, 0U); 182 } 183 184 #if GIC_EXT_INTID 185 for (i = MIN_ESPI_ID; i < num_eints; i += (1U << ICFGR_SHIFT)) { 186 gicd_write_icfgr(gicd_base, i, 0U); 187 } 188 #endif 189 } 190 191 /******************************************************************************* 192 * Helper function to configure properties of secure (E)SPIs 193 ******************************************************************************/ 194 unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, 195 const interrupt_prop_t *interrupt_props, 196 unsigned int interrupt_props_num) 197 { 198 unsigned int i; 199 const interrupt_prop_t *current_prop; 200 unsigned long long gic_affinity_val; 201 unsigned int ctlr_enable = 0U; 202 203 /* Make sure there's a valid property array */ 204 if (interrupt_props_num > 0U) { 205 assert(interrupt_props != NULL); 206 } 207 208 for (i = 0U; i < interrupt_props_num; i++) { 209 current_prop = &interrupt_props[i]; 210 211 unsigned int intr_num = current_prop->intr_num; 212 213 /* Skip SGI, (E)PPI and LPI interrupts */ 214 if (!IS_SPI(intr_num)) { 215 continue; 216 } 217 218 /* Configure this interrupt as a secure interrupt */ 219 gicd_clr_igroupr(gicd_base, intr_num); 220 221 /* Configure this interrupt as G0 or a G1S interrupt */ 222 assert((current_prop->intr_grp == INTR_GROUP0) || 223 (current_prop->intr_grp == INTR_GROUP1S)); 224 225 if (current_prop->intr_grp == INTR_GROUP1S) { 226 gicd_set_igrpmodr(gicd_base, intr_num); 227 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 228 } else { 229 gicd_clr_igrpmodr(gicd_base, intr_num); 230 ctlr_enable |= CTLR_ENABLE_G0_BIT; 231 } 232 233 /* Set interrupt configuration */ 234 gicd_set_icfgr(gicd_base, intr_num, current_prop->intr_cfg); 235 236 /* Set the priority of this interrupt */ 237 gicd_set_ipriorityr(gicd_base, intr_num, 238 current_prop->intr_pri); 239 240 /* Target (E)SPIs to the primary CPU */ 241 gic_affinity_val = 242 gicd_irouter_val_from_mpidr(read_mpidr(), 0U); 243 gicd_write_irouter(gicd_base, intr_num, 244 gic_affinity_val); 245 246 /* Enable this interrupt */ 247 gicd_set_isenabler(gicd_base, intr_num); 248 } 249 250 return ctlr_enable; 251 } 252 253 /******************************************************************************* 254 * Helper function to configure the default attributes of (E)SPIs 255 ******************************************************************************/ 256 void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) 257 { 258 unsigned int i, ppi_regs_num, regs_num; 259 260 #if GIC_EXT_INTID 261 /* Calculate number of PPI registers */ 262 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 263 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 264 /* All other values except PPInum [0-2] are reserved */ 265 if (ppi_regs_num > 3U) { 266 ppi_regs_num = 1U; 267 } 268 #else 269 ppi_regs_num = 1U; 270 #endif 271 /* 272 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 273 * This is a more scalable approach as it avoids clearing 274 * the enable bits in the GICD_CTLR. 275 */ 276 for (i = 0U; i < ppi_regs_num; ++i) { 277 gicr_write_icenabler(gicr_base, i, ~0U); 278 } 279 280 /* Wait for pending writes to GICR_ICENABLER */ 281 gicr_wait_for_pending_write(gicr_base); 282 283 /* 32 interrupt IDs per GICR_IGROUPR register */ 284 for (i = 0U; i < ppi_regs_num; ++i) { 285 /* Treat all SGIs/(E)PPIs as G1NS by default */ 286 gicr_write_igroupr(gicr_base, i, ~0U); 287 } 288 289 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 290 regs_num = ppi_regs_num << 3; 291 for (i = 0U; i < regs_num; ++i) { 292 /* Setup the default (E)PPI/SGI priorities doing 4 at a time */ 293 gicr_write_ipriorityr(gicr_base, i, GICD_IPRIORITYR_DEF_VAL); 294 } 295 296 /* 16 interrupt IDs per GICR_ICFGR register */ 297 regs_num = ppi_regs_num << 1; 298 for (i = (MIN_PPI_ID >> ICFGR_SHIFT); i < regs_num; ++i) { 299 /* Configure all (E)PPIs as level triggered by default */ 300 gicr_write_icfgr(gicr_base, i, 0U); 301 } 302 } 303 304 /******************************************************************************* 305 * Helper function to configure properties of secure G0 and G1S (E)PPIs and SGIs 306 ******************************************************************************/ 307 unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base, 308 const interrupt_prop_t *interrupt_props, 309 unsigned int interrupt_props_num) 310 { 311 unsigned int i; 312 const interrupt_prop_t *current_prop; 313 unsigned int ctlr_enable = 0U; 314 315 /* Make sure there's a valid property array */ 316 if (interrupt_props_num > 0U) { 317 assert(interrupt_props != NULL); 318 } 319 320 for (i = 0U; i < interrupt_props_num; i++) { 321 current_prop = &interrupt_props[i]; 322 323 unsigned int intr_num = current_prop->intr_num; 324 325 /* Skip (E)SPI interrupt */ 326 if (!IS_SGI_PPI(intr_num)) { 327 continue; 328 } 329 330 /* Configure this interrupt as a secure interrupt */ 331 gicr_clr_igroupr(gicr_base, intr_num); 332 333 /* Configure this interrupt as G0 or a G1S interrupt */ 334 assert((current_prop->intr_grp == INTR_GROUP0) || 335 (current_prop->intr_grp == INTR_GROUP1S)); 336 337 if (current_prop->intr_grp == INTR_GROUP1S) { 338 gicr_set_igrpmodr(gicr_base, intr_num); 339 ctlr_enable |= CTLR_ENABLE_G1S_BIT; 340 } else { 341 gicr_clr_igrpmodr(gicr_base, intr_num); 342 ctlr_enable |= CTLR_ENABLE_G0_BIT; 343 } 344 345 /* Set the priority of this interrupt */ 346 gicr_set_ipriorityr(gicr_base, intr_num, 347 current_prop->intr_pri); 348 349 /* 350 * Set interrupt configuration for (E)PPIs. 351 * Configurations for SGIs 0-15 are ignored. 352 */ 353 if (intr_num >= MIN_PPI_ID) { 354 gicr_set_icfgr(gicr_base, intr_num, 355 current_prop->intr_cfg); 356 } 357 358 /* Enable this interrupt */ 359 gicr_set_isenabler(gicr_base, intr_num); 360 } 361 362 return ctlr_enable; 363 } 364 365 /** 366 * gicv3_rdistif_get_number_frames() - determine size of GICv3 GICR region 367 * @gicr_frame: base address of the GICR region to check 368 * 369 * This iterates over the GICR_TYPER registers of multiple GICR frames in 370 * a GICR region, to find the instance which has the LAST bit set. For most 371 * systems this corresponds to the number of cores handled by a redistributor, 372 * but there could be disabled cores among them. 373 * It assumes that each GICR region is fully accessible (till the LAST bit 374 * marks the end of the region). 375 * If a platform has multiple GICR regions, this function would need to be 376 * called multiple times, providing the respective GICR base address each time. 377 * 378 * Return: number of valid GICR frames (at least 1, up to PLATFORM_CORE_COUNT) 379 ******************************************************************************/ 380 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame) 381 { 382 uintptr_t rdistif_base = gicr_frame; 383 unsigned int count; 384 385 for (count = 1U; count < PLATFORM_CORE_COUNT; count++) { 386 uint64_t typer_val = gicr_read_typer(rdistif_base); 387 388 if ((typer_val & TYPER_LAST_BIT) != 0U) { 389 break; 390 } 391 rdistif_base += gicv3_redist_size(typer_val); 392 } 393 394 return count; 395 } 396