1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_SYSTEMMANAGER_H 8 #define SOCFPGA_SYSTEMMANAGER_H 9 10 #include "socfpga_plat_def.h" 11 12 /* System Manager Register Map */ 13 14 #define SOCFPGA_SYSMGR_SDMMC 0x28 15 16 #define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c 17 18 #define SOCFPGA_SYSMGR_EMAC_0 0x44 19 #define SOCFPGA_SYSMGR_EMAC_1 0x48 20 #define SOCFPGA_SYSMGR_EMAC_2 0x4c 21 #define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 22 23 #define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0 24 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4 25 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8 26 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc 27 #define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0 28 #define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4 29 30 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 31 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 32 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 33 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220 34 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224 35 36 /* Field Masking */ 37 38 #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) 39 #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) 40 41 #define IDLE_DATA_LWSOC2FPGA BIT(0) 42 #define IDLE_DATA_SOC2FPGA BIT(4) 43 #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) 44 45 #define SCR_AXI_AP_MASK BIT(24) 46 #define SCR_FPGA2SOC_MASK BIT(16) 47 #define SCR_MPU_MASK BIT(0) 48 #define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \ 49 | SCR_MPU_MASK) 50 #define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 51 52 #define SYSMGR_ECC_OCRAM_MASK BIT(1) 53 #define SYSMGR_ECC_DDR0_MASK BIT(16) 54 #define SYSMGR_ECC_DDR1_MASK BIT(17) 55 56 /* Macros */ 57 58 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ 59 + (SOCFPGA_SYSMGR_##_reg)) 60 61 #define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ 62 + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg)) 63 64 #define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ 65 + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg)) 66 67 /* L3 Interconnect Register Map */ 68 #define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000 69 #define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004 70 #define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c 71 #define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010 72 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c 73 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020 74 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024 75 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028 76 #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c 77 #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030 78 #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034 79 #define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040 80 #define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044 81 #define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048 82 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050 83 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054 84 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058 85 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c 86 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060 87 #define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064 88 #define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068 89 #define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c 90 #define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070 91 92 #define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008 93 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c 94 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010 95 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014 96 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018 97 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c 98 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020 99 #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c 100 #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030 101 #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034 102 #define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038 103 #define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040 104 #define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044 105 #define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048 106 #define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c 107 #define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054 108 #define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058 109 #define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c 110 #define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060 111 #define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064 112 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068 113 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c 114 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 115 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 116 #define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 117 #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 118 #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094 119 120 #define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688 121 #define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628 122 123 void enable_ns_peripheral_access(void); 124 void enable_ns_bridge_access(void); 125 126 #endif /* SOCFPGA_SYSTEMMANAGER_H */ 127