1 /* 2 * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/mmio.h> 8 #include <uart.h> 9 10 static struct mt_uart uart_save_addr[DRV_SUPPORT_UART_PORTS]; 11 12 static const uint32_t uart_base_addr[DRV_SUPPORT_UART_PORTS] = { 13 UART0_BASE, 14 UART1_BASE 15 }; 16 17 void mt_uart_restore(void) 18 { 19 int uart_idx = UART_PORT0; 20 struct mt_uart *uart; 21 unsigned long base; 22 23 /* Must NOT print any debug log before UART restore */ 24 for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS; 25 uart_idx++) { 26 27 uart = &uart_save_addr[uart_idx]; 28 base = uart->base; 29 30 mmio_write_32(UART_LCR(base), UART_LCR_MODE_B); 31 mmio_write_32(UART_EFR(base), uart->registers.efr); 32 mmio_write_32(UART_LCR(base), uart->registers.lcr); 33 mmio_write_32(UART_FCR(base), uart->registers.fcr); 34 35 /* baudrate */ 36 mmio_write_32(UART_HIGHSPEED(base), uart->registers.highspeed); 37 mmio_write_32(UART_FRACDIV_L(base), uart->registers.fracdiv_l); 38 mmio_write_32(UART_FRACDIV_M(base), uart->registers.fracdiv_m); 39 mmio_write_32(UART_LCR(base), 40 uart->registers.lcr | UART_LCR_DLAB); 41 mmio_write_32(UART_DLL(base), uart->registers.dll); 42 mmio_write_32(UART_DLH(base), uart->registers.dlh); 43 mmio_write_32(UART_LCR(base), uart->registers.lcr); 44 mmio_write_32(UART_SAMPLE_COUNT(base), 45 uart->registers.sample_count); 46 mmio_write_32(UART_SAMPLE_POINT(base), 47 uart->registers.sample_point); 48 mmio_write_32(UART_GUARD(base), uart->registers.guard); 49 50 /* flow control */ 51 mmio_write_32(UART_ESCAPE_EN(base), uart->registers.escape_en); 52 mmio_write_32(UART_MCR(base), uart->registers.mcr); 53 mmio_write_32(UART_IER(base), uart->registers.ier); 54 mmio_write_32(UART_SCR(base), uart->registers.scr); 55 } 56 } 57 58 void mt_uart_save(void) 59 { 60 int uart_idx = UART_PORT0; 61 struct mt_uart *uart; 62 unsigned long base; 63 64 for (uart_idx = UART_PORT0; uart_idx < HW_SUPPORT_UART_PORTS; 65 uart_idx++) { 66 67 uart_save_addr[uart_idx].base = uart_base_addr[uart_idx]; 68 base = uart_base_addr[uart_idx]; 69 uart = &uart_save_addr[uart_idx]; 70 uart->registers.lcr = mmio_read_32(UART_LCR(base)); 71 72 mmio_write_32(UART_LCR(base), UART_LCR_MODE_B); 73 uart->registers.efr = mmio_read_32(UART_EFR(base)); 74 mmio_write_32(UART_LCR(base), uart->registers.lcr); 75 uart->registers.fcr = mmio_read_32(UART_FCR_RD(base)); 76 77 /* baudrate */ 78 uart->registers.highspeed = mmio_read_32(UART_HIGHSPEED(base)); 79 uart->registers.fracdiv_l = mmio_read_32(UART_FRACDIV_L(base)); 80 uart->registers.fracdiv_m = mmio_read_32(UART_FRACDIV_M(base)); 81 mmio_write_32(UART_LCR(base), 82 uart->registers.lcr | UART_LCR_DLAB); 83 uart->registers.dll = mmio_read_32(UART_DLL(base)); 84 uart->registers.dlh = mmio_read_32(UART_DLH(base)); 85 mmio_write_32(UART_LCR(base), uart->registers.lcr); 86 uart->registers.sample_count = mmio_read_32( 87 UART_SAMPLE_COUNT(base)); 88 uart->registers.sample_point = mmio_read_32( 89 UART_SAMPLE_POINT(base)); 90 uart->registers.guard = mmio_read_32(UART_GUARD(base)); 91 92 /* flow control */ 93 uart->registers.escape_en = mmio_read_32(UART_ESCAPE_EN(base)); 94 uart->registers.mcr = mmio_read_32(UART_MCR(base)); 95 uart->registers.ier = mmio_read_32(UART_IER(base)); 96 uart->registers.scr = mmio_read_32(UART_SCR(base)); 97 } 98 } 99 100 void mt_console_uart_cg(int on) 101 { 102 if (on == 1) { 103 mmio_write_32(UART_CLOCK_GATE_CLR, UART0_CLOCK_GATE_BIT); 104 } else { 105 mmio_write_32(UART_CLOCK_GATE_SET, UART0_CLOCK_GATE_BIT); 106 } 107 } 108 109 uint32_t mt_console_uart_cg_status(void) 110 { 111 return mmio_read_32(UART_CLOCK_GATE_STA) & UART0_CLOCK_GATE_BIT; 112 } 113