1 /* 2 * Copyright 2020-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/arm/tzc380.h> 15 #include <drivers/console.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <gpc.h> 23 #include <imx_aipstz.h> 24 #include <imx_uart.h> 25 #include <imx_rdc.h> 26 #include <imx8m_caam.h> 27 #include <imx8m_csu.h> 28 #include <platform_def.h> 29 #include <plat_imx8.h> 30 31 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 32 33 static const mmap_region_t imx_mmap[] = { 34 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, 35 NOC_MAP, {0}, 36 }; 37 38 static const struct aipstz_cfg aipstz[] = { 39 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 40 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 41 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 42 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, 43 {0}, 44 }; 45 46 static const struct imx_rdc_cfg rdc[] = { 47 /* Master domain assignment */ 48 RDC_MDAn(RDC_MDA_M7, DID1), 49 50 /* peripherals domain permission */ 51 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W), 52 53 /* memory region */ 54 55 /* Sentinel */ 56 {0}, 57 }; 58 59 static const struct imx_csu_cfg csu_cfg[] = { 60 /* peripherals csl setting */ 61 CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, UNLOCKED), 62 CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, UNLOCKED), 63 64 /* master HP0~1 */ 65 66 /* SA setting */ 67 68 /* HP control setting */ 69 70 /* Sentinel */ 71 {0} 72 }; 73 74 static entry_point_info_t bl32_image_ep_info; 75 static entry_point_info_t bl33_image_ep_info; 76 77 /* get SPSR for BL33 entry */ 78 static uint32_t get_spsr_for_bl33_entry(void) 79 { 80 unsigned long el_status; 81 unsigned long mode; 82 uint32_t spsr; 83 84 /* figure out what mode we enter the non-secure world */ 85 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 86 el_status &= ID_AA64PFR0_ELX_MASK; 87 88 mode = (el_status) ? MODE_EL2 : MODE_EL1; 89 90 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 91 return spsr; 92 } 93 94 static void bl31_tzc380_setup(void) 95 { 96 unsigned int val; 97 98 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); 99 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) 100 return; 101 102 tzc380_init(IMX_TZASC_BASE); 103 104 /* 105 * Need to substact offset 0x40000000 from CPU address when 106 * programming tzasc region for i.mx8mp. 107 */ 108 109 /* Enable 1G-5G S/NS RW */ 110 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | 111 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 112 } 113 114 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 115 u_register_t arg2, u_register_t arg3) 116 { 117 static console_t console; 118 unsigned int val; 119 unsigned int i; 120 121 /* Enable CSU NS access permission */ 122 for (i = 0; i < 64; i++) { 123 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); 124 } 125 126 imx_aipstz_init(aipstz); 127 128 imx_rdc_init(rdc); 129 130 imx_csu_init(csu_cfg); 131 132 /* config the ocram memory range for secure access */ 133 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4E1); 134 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); 135 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 136 137 imx8m_caam_init(); 138 139 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 140 IMX_CONSOLE_BAUDRATE, &console); 141 /* This console is only used for boot stage */ 142 console_set_scope(&console, CONSOLE_FLAG_BOOT); 143 144 /* 145 * tell BL3-1 where the non-secure software image is located 146 * and the entry state information. 147 */ 148 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 149 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 150 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 151 152 #if defined(SPD_opteed) || defined(SPD_trusty) 153 /* Populate entry point information for BL32 */ 154 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 155 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 156 bl32_image_ep_info.pc = BL32_BASE; 157 bl32_image_ep_info.spsr = 0; 158 159 /* Pass TEE base and size to bl33 */ 160 bl33_image_ep_info.args.arg1 = BL32_BASE; 161 bl33_image_ep_info.args.arg2 = BL32_SIZE; 162 163 #ifdef SPD_trusty 164 bl32_image_ep_info.args.arg0 = BL32_SIZE; 165 bl32_image_ep_info.args.arg1 = BL32_BASE; 166 #else 167 /* Make sure memory is clean */ 168 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 169 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 170 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 171 #endif 172 #endif 173 174 bl31_tzc380_setup(); 175 } 176 177 void bl31_plat_arch_setup(void) 178 { 179 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE), 180 MT_MEMORY | MT_RW | MT_SECURE); 181 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE), 182 MT_MEMORY | MT_RO | MT_SECURE); 183 #if USE_COHERENT_MEM 184 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 185 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), 186 MT_DEVICE | MT_RW | MT_SECURE); 187 #endif 188 189 /* Map TEE memory */ 190 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); 191 192 mmap_add(imx_mmap); 193 194 init_xlat_tables(); 195 196 enable_mmu_el3(0); 197 } 198 199 void bl31_platform_setup(void) 200 { 201 generic_delay_timer_init(); 202 203 /* select the CKIL source to 32K OSC */ 204 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1); 205 206 plat_gic_driver_init(); 207 plat_gic_init(); 208 209 imx_gpc_init(); 210 } 211 212 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 213 { 214 if (type == NON_SECURE) { 215 return &bl33_image_ep_info; 216 } 217 218 if (type == SECURE) { 219 return &bl32_image_ep_info; 220 } 221 222 return NULL; 223 } 224 225 unsigned int plat_get_syscnt_freq2(void) 226 { 227 return COUNTER_FREQUENCY; 228 } 229 230 #ifdef SPD_trusty 231 void plat_trusty_set_boot_args(aapcs64_params_t *args) 232 { 233 args->arg0 = BL32_SIZE; 234 args->arg1 = BL32_BASE; 235 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 236 } 237 #endif 238