1 /* 2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef NEOVERSE_N2_H 8 #define NEOVERSE_N2_H 9 10 /* Neoverse N2 ID register for revision r0p0 */ 11 #define NEOVERSE_N2_MIDR U(0x410FD490) 12 13 /******************************************************************************* 14 * CPU Power control register 15 ******************************************************************************/ 16 #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 17 #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) 18 19 /******************************************************************************* 20 * CPU Extended Control register specific definitions. 21 ******************************************************************************/ 22 #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 23 #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) 24 #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 25 26 /******************************************************************************* 27 * CPU Auxiliary Control register specific definitions. 28 ******************************************************************************/ 29 #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 30 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 31 32 /******************************************************************************* 33 * CPU Auxiliary Control register 2 specific definitions. 34 ******************************************************************************/ 35 #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 36 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 37 38 /******************************************************************************* 39 * CPU Auxiliary Control register 5 specific definitions. 40 ******************************************************************************/ 41 #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 42 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 43 44 /******************************************************************************* 45 * CPU Auxiliary Control register specific definitions. 46 ******************************************************************************/ 47 #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 48 #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 49 #define CPUECTLR2_EL1_PF_MODE_LSB U(11) 50 #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 51 52 #endif /* NEOVERSE_N2_H */ 53