1/* 2 * Copyright (c) 2019-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if WORKAROUND_CVE_2022_23960 26 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1 27#endif /* WORKAROUND_CVE_2022_23960 */ 28 29 /* -------------------------------------------------- 30 * Errata Workaround for Neoverse V1 Errata #1774420. 31 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 32 * x0: variant[4:7] and revision[0:3] of current cpu. 33 * Shall clobber: x0-x17 34 * -------------------------------------------------- 35 */ 36func errata_neoverse_v1_1774420_wa 37 /* Check workaround compatibility. */ 38 mov x17, x30 39 bl check_errata_1774420 40 cbz x0, 1f 41 42 /* Set bit 53 in CPUECTLR_EL1 */ 43 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 44 orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53 45 msr NEOVERSE_V1_CPUECTLR_EL1, x1 46 isb 471: 48 ret x17 49endfunc errata_neoverse_v1_1774420_wa 50 51func check_errata_1774420 52 /* Applies to r0p0 and r1p0. */ 53 mov x1, #0x10 54 b cpu_rev_var_ls 55endfunc check_errata_1774420 56 57 /* -------------------------------------------------- 58 * Errata Workaround for Neoverse V1 Errata #1791573. 59 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 60 * x0: variant[4:7] and revision[0:3] of current cpu. 61 * Shall clobber: x0-x17 62 * -------------------------------------------------- 63 */ 64func errata_neoverse_v1_1791573_wa 65 /* Check workaround compatibility. */ 66 mov x17, x30 67 bl check_errata_1791573 68 cbz x0, 1f 69 70 /* Set bit 2 in ACTLR2_EL1 */ 71 mrs x1, NEOVERSE_V1_ACTLR2_EL1 72 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 73 msr NEOVERSE_V1_ACTLR2_EL1, x1 74 isb 751: 76 ret x17 77endfunc errata_neoverse_v1_1791573_wa 78 79func check_errata_1791573 80 /* Applies to r0p0 and r1p0. */ 81 mov x1, #0x10 82 b cpu_rev_var_ls 83endfunc check_errata_1791573 84 85 /* -------------------------------------------------- 86 * Errata Workaround for Neoverse V1 Errata #1852267. 87 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 88 * x0: variant[4:7] and revision[0:3] of current cpu. 89 * Shall clobber: x0-x17 90 * -------------------------------------------------- 91 */ 92func errata_neoverse_v1_1852267_wa 93 /* Check workaround compatibility. */ 94 mov x17, x30 95 bl check_errata_1852267 96 cbz x0, 1f 97 98 /* Set bit 28 in ACTLR2_EL1 */ 99 mrs x1, NEOVERSE_V1_ACTLR2_EL1 100 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28 101 msr NEOVERSE_V1_ACTLR2_EL1, x1 102 isb 1031: 104 ret x17 105endfunc errata_neoverse_v1_1852267_wa 106 107func check_errata_1852267 108 /* Applies to r0p0 and r1p0. */ 109 mov x1, #0x10 110 b cpu_rev_var_ls 111endfunc check_errata_1852267 112 113 /* -------------------------------------------------- 114 * Errata Workaround for Neoverse V1 Errata #1925756. 115 * This applies to revisions <= r1p1. 116 * x0: variant[4:7] and revision[0:3] of current cpu. 117 * Shall clobber: x0-x17 118 * -------------------------------------------------- 119 */ 120func errata_neoverse_v1_1925756_wa 121 /* Check workaround compatibility. */ 122 mov x17, x30 123 bl check_errata_1925756 124 cbz x0, 1f 125 126 /* Set bit 8 in CPUECTLR_EL1 */ 127 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 128 orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8 129 msr NEOVERSE_V1_CPUECTLR_EL1, x1 130 isb 1311: 132 ret x17 133endfunc errata_neoverse_v1_1925756_wa 134 135func check_errata_1925756 136 /* Applies to <= r1p1. */ 137 mov x1, #0x11 138 b cpu_rev_var_ls 139endfunc check_errata_1925756 140 141 /* -------------------------------------------------- 142 * Errata Workaround for Neoverse V1 Erratum #1940577 143 * This applies to revisions r1p0 - r1p1 and is open. 144 * It also exists in r0p0 but there is no fix in that 145 * revision. 146 * Inputs: 147 * x0: variant[4:7] and revision[0:3] of current cpu. 148 * Shall clobber: x0-x17 149 * -------------------------------------------------- 150 */ 151func errata_neoverse_v1_1940577_wa 152 /* Compare x0 against revisions r1p0 - r1p1 */ 153 mov x17, x30 154 bl check_errata_1940577 155 cbz x0, 1f 156 157 mov x0, #0 158 msr S3_6_C15_C8_0, x0 159 ldr x0, =0x10E3900002 160 msr S3_6_C15_C8_2, x0 161 ldr x0, =0x10FFF00083 162 msr S3_6_C15_C8_3, x0 163 ldr x0, =0x2001003FF 164 msr S3_6_C15_C8_1, x0 165 166 mov x0, #1 167 msr S3_6_C15_C8_0, x0 168 ldr x0, =0x10E3800082 169 msr S3_6_C15_C8_2, x0 170 ldr x0, =0x10FFF00083 171 msr S3_6_C15_C8_3, x0 172 ldr x0, =0x2001003FF 173 msr S3_6_C15_C8_1, x0 174 175 mov x0, #2 176 msr S3_6_C15_C8_0, x0 177 ldr x0, =0x10E3800200 178 msr S3_6_C15_C8_2, x0 179 ldr x0, =0x10FFF003E0 180 msr S3_6_C15_C8_3, x0 181 ldr x0, =0x2001003FF 182 msr S3_6_C15_C8_1, x0 183 184 isb 1851: 186 ret x17 187endfunc errata_neoverse_v1_1940577_wa 188 189func check_errata_1940577 190 /* Applies to revisions r1p0 - r1p1. */ 191 mov x1, #0x10 192 mov x2, #0x11 193 b cpu_rev_var_range 194endfunc check_errata_1940577 195 196 /* -------------------------------------------------- 197 * Errata Workaround for Neoverse V1 Errata #1966096 198 * This applies to revisions r1p0 - r1p1 and is open. 199 * It also exists in r0p0 but there is no workaround 200 * for that revision. 201 * x0: variant[4:7] and revision[0:3] of current cpu. 202 * Shall clobber: x0-x17 203 * -------------------------------------------------- 204 */ 205func errata_neoverse_v1_1966096_wa 206 /* Check workaround compatibility. */ 207 mov x17, x30 208 bl check_errata_1966096 209 cbz x0, 1f 210 211 /* Apply the workaround. */ 212 mov x0, #0x3 213 msr S3_6_C15_C8_0, x0 214 ldr x0, =0xEE010F12 215 msr S3_6_C15_C8_2, x0 216 ldr x0, =0xFFFF0FFF 217 msr S3_6_C15_C8_3, x0 218 ldr x0, =0x80000000003FF 219 msr S3_6_C15_C8_1, x0 220 isb 221 2221: 223 ret x17 224endfunc errata_neoverse_v1_1966096_wa 225 226func check_errata_1966096 227 mov x1, #0x10 228 mov x2, #0x11 229 b cpu_rev_var_range 230endfunc check_errata_1966096 231 232 /* -------------------------------------------------- 233 * Errata Workaround for Neoverse V1 Errata #2139242. 234 * This applies to revisions r0p0, r1p0, and r1p1, it 235 * is still open. 236 * x0: variant[4:7] and revision[0:3] of current cpu. 237 * Shall clobber: x0-x17 238 * -------------------------------------------------- 239 */ 240func errata_neoverse_v1_2139242_wa 241 /* Check workaround compatibility. */ 242 mov x17, x30 243 bl check_errata_2139242 244 cbz x0, 1f 245 246 /* Apply the workaround. */ 247 mov x0, #0x3 248 msr S3_6_C15_C8_0, x0 249 ldr x0, =0xEE720F14 250 msr S3_6_C15_C8_2, x0 251 ldr x0, =0xFFFF0FDF 252 msr S3_6_C15_C8_3, x0 253 ldr x0, =0x40000005003FF 254 msr S3_6_C15_C8_1, x0 255 isb 256 2571: 258 ret x17 259endfunc errata_neoverse_v1_2139242_wa 260 261func check_errata_2139242 262 /* Applies to r0p0, r1p0, r1p1 */ 263 mov x1, #0x11 264 b cpu_rev_var_ls 265endfunc check_errata_2139242 266 267 /* -------------------------------------------------- 268 * Errata Workaround for Neoverse V1 Errata #2108267. 269 * This applies to revisions r0p0, r1p0, and r1p1, it 270 * is still open. 271 * x0: variant[4:7] and revision[0:3] of current cpu. 272 * Shall clobber: x0-x1, x17 273 * -------------------------------------------------- 274 */ 275func errata_neoverse_v1_2108267_wa 276 /* Check workaround compatibility. */ 277 mov x17, x30 278 bl check_errata_2108267 279 cbz x0, 1f 280 281 /* Apply the workaround. */ 282 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 283 mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV 284 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH 285 msr NEOVERSE_V1_CPUECTLR_EL1, x1 2861: 287 ret x17 288endfunc errata_neoverse_v1_2108267_wa 289 290func check_errata_2108267 291 /* Applies to r0p0, r1p0, r1p1 */ 292 mov x1, #0x11 293 b cpu_rev_var_ls 294endfunc check_errata_2108267 295 296 /* -------------------------------------------------- 297 * Errata Workaround for Neoverse V1 Errata #2216392. 298 * This applies to revisions r1p0 and r1p1 and is 299 * still open. 300 * This issue is also present in r0p0 but there is no 301 * workaround in that revision. 302 * x0: variant[4:7] and revision[0:3] of current cpu. 303 * Shall clobber: x0-x17 304 * -------------------------------------------------- 305 */ 306func errata_neoverse_v1_2216392_wa 307 /* Check workaround compatibility. */ 308 mov x17, x30 309 bl check_errata_2216392 310 cbz x0, 1f 311 312 ldr x0, =0x5 313 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 314 ldr x0, =0x10F600E000 315 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 316 ldr x0, =0x10FF80E000 317 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 318 ldr x0, =0x80000000003FF 319 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 320 321 isb 3221: 323 ret x17 324endfunc errata_neoverse_v1_2216392_wa 325 326func check_errata_2216392 327 /* Applies to revisions r1p0 and r1p1. */ 328 mov x1, #CPU_REV(1, 0) 329 mov x2, #CPU_REV(1, 1) 330 b cpu_rev_var_range 331endfunc check_errata_2216392 332 333func check_errata_cve_2022_23960 334#if WORKAROUND_CVE_2022_23960 335 mov x0, #ERRATA_APPLIES 336#else 337 mov x0, #ERRATA_MISSING 338#endif 339 ret 340endfunc check_errata_cve_2022_23960 341 342 /* --------------------------------------------- 343 * HW will do the cache maintenance while powering down 344 * --------------------------------------------- 345 */ 346func neoverse_v1_core_pwr_dwn 347 /* --------------------------------------------- 348 * Enable CPU power down bit in power control register 349 * --------------------------------------------- 350 */ 351 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 352 orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 353 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 354 isb 355 ret 356endfunc neoverse_v1_core_pwr_dwn 357 358 /* 359 * Errata printing function for Neoverse V1. Must follow AAPCS. 360 */ 361#if REPORT_ERRATA 362func neoverse_v1_errata_report 363 stp x8, x30, [sp, #-16]! 364 365 bl cpu_get_rev_var 366 mov x8, x0 367 368 /* 369 * Report all errata. The revision-variant information is passed to 370 * checking functions of each errata. 371 */ 372 report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 373 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 374 report_errata ERRATA_V1_1852267, neoverse_v1, 1852267 375 report_errata ERRATA_V1_1925756, neoverse_v1, 1925756 376 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 377 report_errata ERRATA_V1_1966096, neoverse_v1, 1966096 378 report_errata ERRATA_V1_2139242, neoverse_v1, 2139242 379 report_errata ERRATA_V1_2108267, neoverse_v1, 2108267 380 report_errata ERRATA_V1_2216392, neoverse_v1, 2216392 381 report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960 382 383 ldp x8, x30, [sp], #16 384 ret 385endfunc neoverse_v1_errata_report 386#endif 387 388func neoverse_v1_reset_func 389 mov x19, x30 390 391 /* Disable speculative loads */ 392 msr SSBS, xzr 393 isb 394 395#if ERRATA_V1_1774420 396 mov x0, x18 397 bl errata_neoverse_v1_1774420_wa 398#endif 399 400#if ERRATA_V1_1791573 401 mov x0, x18 402 bl errata_neoverse_v1_1791573_wa 403#endif 404 405#if ERRATA_V1_1852267 406 mov x0, x18 407 bl errata_neoverse_v1_1852267_wa 408#endif 409 410#if ERRATA_V1_1925756 411 mov x0, x18 412 bl errata_neoverse_v1_1925756_wa 413#endif 414 415#if ERRATA_V1_1940577 416 mov x0, x18 417 bl errata_neoverse_v1_1940577_wa 418#endif 419 420#if ERRATA_V1_1966096 421 mov x0, x18 422 bl errata_neoverse_v1_1966096_wa 423#endif 424 425#if ERRATA_V1_2139242 426 mov x0, x18 427 bl errata_neoverse_v1_2139242_wa 428#endif 429 430#if ERRATA_V1_2108267 431 mov x0, x18 432 bl errata_neoverse_v1_2108267_wa 433#endif 434 435#if ERRATA_V1_2216392 436 mov x0, x18 437 bl errata_neoverse_v1_2216392_wa 438#endif 439 440#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 441 /* 442 * The Neoverse-V1 generic vectors are overridden to apply errata 443 * mitigation on exception entry from lower ELs. 444 */ 445 adr x0, wa_cve_vbar_neoverse_v1 446 msr vbar_el3, x0 447#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 448 449 isb 450 ret x19 451endfunc neoverse_v1_reset_func 452 453 /* --------------------------------------------- 454 * This function provides Neoverse-V1 specific 455 * register information for crash reporting. 456 * It needs to return with x6 pointing to 457 * a list of register names in ascii and 458 * x8 - x15 having values of registers to be 459 * reported. 460 * --------------------------------------------- 461 */ 462.section .rodata.neoverse_v1_regs, "aS" 463neoverse_v1_regs: /* The ascii list of register names to be reported */ 464 .asciz "cpuectlr_el1", "" 465 466func neoverse_v1_cpu_reg_dump 467 adr x6, neoverse_v1_regs 468 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 469 ret 470endfunc neoverse_v1_cpu_reg_dump 471 472declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 473 neoverse_v1_reset_func, \ 474 neoverse_v1_core_pwr_dwn 475