1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2022, STMicroelectronics - All Rights Reserved 4 */ 5 6#include <common/tbbr/tbbr_img_def.h> 7#include <dt-bindings/soc/stm32mp13-tzc400.h> 8 9#include <platform_def.h> 10 11#ifndef DDR_SIZE 12#error "DDR_SIZE is not defined" 13#endif 14 15#define DDR_NS_BASE STM32MP_DDR_BASE 16#define DDR_SEC_SIZE 0x01e00000 17#define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE)) 18#define DDR_SHARE_SIZE 0x00200000 19#define DDR_SHARE_BASE (DDR_SEC_BASE - DDR_SHARE_SIZE) 20#define DDR_NS_SIZE (DDR_SHARE_BASE - DDR_NS_BASE) 21 22/dts-v1/; 23 24/ { 25 dtb-registry { 26 compatible = "fconf,dyn_cfg-dtb_registry"; 27 28 hw-config { 29 load-address = <0x0 STM32MP_HW_CONFIG_BASE>; 30 max-size = <STM32MP_HW_CONFIG_MAX_SIZE>; 31 id = <HW_CONFIG_ID>; 32 }; 33 34 nt_fw { 35 load-address = <0x0 STM32MP_BL33_BASE>; 36 max-size = <STM32MP_BL33_MAX_SIZE>; 37 id = <BL33_IMAGE_ID>; 38 }; 39 40 tos_fw { 41 load-address = <0x0 DDR_SEC_BASE>; 42 max-size = <DDR_SEC_SIZE>; 43 id = <BL32_IMAGE_ID>; 44 }; 45 }; 46 47 st-mem-firewall { 48 compatible = "st,mem-firewall"; 49 memory-ranges = < 50 DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR 51 DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE 52 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) 53 DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0>; 54 }; 55}; 56