1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/arm/gicv2.h> 14 #include <lib/mmio.h> 15 #include <lib/psci/psci.h> 16 #include <plat/arm/common/plat_arm.h> 17 #include <plat/common/platform.h> 18 19 #include <plat_private.h> 20 #include "pm_client.h" 21 #include "zynqmp_pm_api_sys.h" 22 23 static uintptr_t zynqmp_sec_entry; 24 25 static void zynqmp_cpu_standby(plat_local_state_t cpu_state) 26 { 27 VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); 28 29 dsb(); 30 wfi(); 31 } 32 33 static int32_t zynqmp_pwr_domain_on(u_register_t mpidr) 34 { 35 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 36 const struct pm_proc *proc; 37 uint32_t buff[3]; 38 enum pm_ret_status ret; 39 40 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); 41 42 if (cpu_id == -1) { 43 return PSCI_E_INTERN_FAIL; 44 } 45 proc = pm_get_proc(cpu_id); 46 47 /* Check the APU proc status before wakeup */ 48 ret = pm_get_node_status(proc->node_id, buff); 49 if ((ret != PM_RET_SUCCESS) || (buff[0] == PM_PROC_STATE_SUSPENDING)) { 50 return PSCI_E_INTERN_FAIL; 51 } 52 53 /* Clear power down request */ 54 pm_client_wakeup(proc); 55 56 /* Send request to PMU to wake up selected APU CPU core */ 57 pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING); 58 59 return PSCI_E_SUCCESS; 60 } 61 62 static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state) 63 { 64 uint32_t cpu_id = plat_my_core_pos(); 65 const struct pm_proc *proc = pm_get_proc(cpu_id); 66 67 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 68 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 69 __func__, i, target_state->pwr_domain_state[i]); 70 } 71 72 /* Prevent interrupts from spuriously waking up this cpu */ 73 gicv2_cpuif_disable(); 74 75 /* 76 * Send request to PMU to power down the appropriate APU CPU 77 * core. 78 * According to PSCI specification, CPU_off function does not 79 * have resume address and CPU core can only be woken up 80 * invoking CPU_on function, during which resume address will 81 * be set. 82 */ 83 pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0); 84 } 85 86 static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) 87 { 88 uint32_t state; 89 uint32_t cpu_id = plat_my_core_pos(); 90 const struct pm_proc *proc = pm_get_proc(cpu_id); 91 92 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) 93 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 94 __func__, i, target_state->pwr_domain_state[i]); 95 96 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? 97 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 98 99 /* Send request to PMU to suspend this core */ 100 pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry); 101 102 /* APU is to be turned off */ 103 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 104 /* disable coherency */ 105 plat_arm_interconnect_exit_coherency(); 106 } 107 } 108 109 static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) 110 { 111 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 112 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 113 __func__, i, target_state->pwr_domain_state[i]); 114 } 115 plat_arm_gic_pcpu_init(); 116 gicv2_cpuif_enable(); 117 } 118 119 static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 120 { 121 uint32_t cpu_id = plat_my_core_pos(); 122 const struct pm_proc *proc = pm_get_proc(cpu_id); 123 124 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 125 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 126 __func__, i, target_state->pwr_domain_state[i]); 127 } 128 129 /* Clear the APU power control register for this cpu */ 130 pm_client_wakeup(proc); 131 132 /* enable coherency */ 133 plat_arm_interconnect_enter_coherency(); 134 /* APU was turned off */ 135 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 136 plat_arm_gic_init(); 137 } else { 138 gicv2_cpuif_enable(); 139 gicv2_pcpu_distif_init(); 140 } 141 } 142 143 /******************************************************************************* 144 * ZynqMP handlers to shutdown/reboot the system 145 ******************************************************************************/ 146 147 static void __dead2 zynqmp_system_off(void) 148 { 149 /* disable coherency */ 150 plat_arm_interconnect_exit_coherency(); 151 152 /* Send the power down request to the PMU */ 153 pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN, 154 pm_get_shutdown_scope()); 155 156 while (1) { 157 wfi(); 158 } 159 } 160 161 static void __dead2 zynqmp_system_reset(void) 162 { 163 /* disable coherency */ 164 plat_arm_interconnect_exit_coherency(); 165 166 /* Send the system reset request to the PMU */ 167 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, 168 pm_get_shutdown_scope()); 169 170 while (1) { 171 wfi(); 172 } 173 } 174 175 static int32_t zynqmp_validate_power_state(uint32_t power_state, 176 psci_power_state_t *req_state) 177 { 178 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 179 180 uint32_t pstate = psci_get_pstate_type(power_state); 181 182 assert(req_state); 183 184 /* Sanity check the requested state */ 185 if (pstate == PSTATE_TYPE_STANDBY) { 186 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 187 } else { 188 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 189 } 190 /* We expect the 'state id' to be zero */ 191 if (psci_get_pstate_id(power_state)) { 192 return PSCI_E_INVALID_PARAMS; 193 } 194 195 return PSCI_E_SUCCESS; 196 } 197 198 static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) 199 { 200 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; 201 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; 202 } 203 204 /******************************************************************************* 205 * Export the platform handlers to enable psci to invoke them 206 ******************************************************************************/ 207 static const struct plat_psci_ops zynqmp_psci_ops = { 208 .cpu_standby = zynqmp_cpu_standby, 209 .pwr_domain_on = zynqmp_pwr_domain_on, 210 .pwr_domain_off = zynqmp_pwr_domain_off, 211 .pwr_domain_suspend = zynqmp_pwr_domain_suspend, 212 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, 213 .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, 214 .system_off = zynqmp_system_off, 215 .system_reset = zynqmp_system_reset, 216 .validate_power_state = zynqmp_validate_power_state, 217 .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, 218 }; 219 220 /******************************************************************************* 221 * Export the platform specific power ops. 222 ******************************************************************************/ 223 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 224 const struct plat_psci_ops **psci_ops) 225 { 226 zynqmp_sec_entry = sec_entrypoint; 227 228 *psci_ops = &zynqmp_psci_ops; 229 230 return 0; 231 } 232