1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/fwu/fwu.h> 14 #include <drivers/fwu/fwu_metadata.h> 15 #include <drivers/io/io_block.h> 16 #include <drivers/io/io_driver.h> 17 #include <drivers/io/io_encrypted.h> 18 #include <drivers/io/io_fip.h> 19 #include <drivers/io/io_memmap.h> 20 #include <drivers/io/io_mtd.h> 21 #include <drivers/io/io_storage.h> 22 #include <drivers/mmc.h> 23 #include <drivers/partition/efi.h> 24 #include <drivers/partition/partition.h> 25 #include <drivers/raw_nand.h> 26 #include <drivers/spi_nand.h> 27 #include <drivers/spi_nor.h> 28 #include <drivers/st/stm32_fmc2_nand.h> 29 #include <drivers/st/stm32_qspi.h> 30 #include <drivers/st/stm32_sdmmc2.h> 31 #include <drivers/usb_device.h> 32 #include <lib/fconf/fconf.h> 33 #include <lib/mmio.h> 34 #include <lib/utils.h> 35 #include <plat/common/platform.h> 36 #include <tools_share/firmware_image_package.h> 37 38 #include <platform_def.h> 39 #include <stm32cubeprogrammer.h> 40 #include <stm32mp_efi.h> 41 #include <stm32mp_fconf_getter.h> 42 #include <stm32mp_io_storage.h> 43 #include <usb_dfu.h> 44 45 /* IO devices */ 46 uintptr_t fip_dev_handle; 47 uintptr_t storage_dev_handle; 48 49 static const io_dev_connector_t *fip_dev_con; 50 51 #ifndef DECRYPTION_SUPPORT_none 52 static const io_dev_connector_t *enc_dev_con; 53 uintptr_t enc_dev_handle; 54 #endif 55 56 #if STM32MP_SDMMC || STM32MP_EMMC 57 static struct mmc_device_info mmc_info; 58 59 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 60 61 static io_block_dev_spec_t mmc_block_dev_spec = { 62 /* It's used as temp buffer in block driver */ 63 .buffer = { 64 .offset = (size_t)&block_buffer, 65 .length = MMC_BLOCK_SIZE, 66 }, 67 .ops = { 68 .read = mmc_read_blocks, 69 .write = NULL, 70 }, 71 .block_size = MMC_BLOCK_SIZE, 72 }; 73 74 static const io_dev_connector_t *mmc_dev_con; 75 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 76 77 #if STM32MP_SPI_NOR 78 static io_mtd_dev_spec_t spi_nor_dev_spec = { 79 .ops = { 80 .init = spi_nor_init, 81 .read = spi_nor_read, 82 }, 83 }; 84 #endif 85 86 #if STM32MP_RAW_NAND 87 static io_mtd_dev_spec_t nand_dev_spec = { 88 .ops = { 89 .init = nand_raw_init, 90 .read = nand_read, 91 .seek = nand_seek_bb 92 }, 93 }; 94 95 static const io_dev_connector_t *nand_dev_con; 96 #endif 97 98 #if STM32MP_SPI_NAND 99 static io_mtd_dev_spec_t spi_nand_dev_spec = { 100 .ops = { 101 .init = spi_nand_init, 102 .read = nand_read, 103 .seek = nand_seek_bb 104 }, 105 }; 106 #endif 107 108 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 109 static const io_dev_connector_t *spi_dev_con; 110 #endif 111 112 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 113 static const io_dev_connector_t *memmap_dev_con; 114 #endif 115 116 io_block_spec_t image_block_spec = { 117 .offset = 0U, 118 .length = 0U, 119 }; 120 121 int open_fip(const uintptr_t spec) 122 { 123 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); 124 } 125 126 #ifndef DECRYPTION_SUPPORT_none 127 int open_enc_fip(const uintptr_t spec) 128 { 129 int result; 130 uintptr_t local_image_handle; 131 132 result = io_dev_init(enc_dev_handle, (uintptr_t)ENC_IMAGE_ID); 133 if (result != 0) { 134 return result; 135 } 136 137 result = io_open(enc_dev_handle, spec, &local_image_handle); 138 if (result != 0) { 139 return result; 140 } 141 142 VERBOSE("Using encrypted FIP\n"); 143 io_close(local_image_handle); 144 145 return 0; 146 } 147 #endif 148 149 int open_storage(const uintptr_t spec) 150 { 151 return io_dev_init(storage_dev_handle, 0); 152 } 153 154 #if STM32MP_EMMC_BOOT 155 static uint32_t get_boot_part_fip_header(void) 156 { 157 io_block_spec_t emmc_boot_fip_block_spec = { 158 .offset = STM32MP_EMMC_BOOT_FIP_OFFSET, 159 .length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */ 160 }; 161 uint32_t magic = 0U; 162 int io_result; 163 size_t bytes_read; 164 uintptr_t fip_hdr_handle; 165 166 io_result = io_open(storage_dev_handle, (uintptr_t)&emmc_boot_fip_block_spec, 167 &fip_hdr_handle); 168 assert(io_result == 0); 169 170 io_result = io_read(fip_hdr_handle, (uintptr_t)&magic, sizeof(magic), 171 &bytes_read); 172 if ((io_result != 0) || (bytes_read != sizeof(magic))) { 173 panic(); 174 } 175 176 io_close(fip_hdr_handle); 177 178 VERBOSE("%s: eMMC boot magic at offset 256K: %08x\n", 179 __func__, magic); 180 181 return magic; 182 } 183 #endif 184 185 static void print_boot_device(boot_api_context_t *boot_context) 186 { 187 switch (boot_context->boot_interface_selected) { 188 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 189 INFO("Using SDMMC\n"); 190 break; 191 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 192 INFO("Using EMMC\n"); 193 break; 194 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 195 INFO("Using QSPI NOR\n"); 196 break; 197 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 198 INFO("Using FMC NAND\n"); 199 break; 200 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 201 INFO("Using SPI NAND\n"); 202 break; 203 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 204 INFO("Using UART\n"); 205 break; 206 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 207 INFO("Using USB\n"); 208 break; 209 default: 210 ERROR("Boot interface %u not found\n", 211 boot_context->boot_interface_selected); 212 panic(); 213 break; 214 } 215 216 if (boot_context->boot_interface_instance != 0U) { 217 INFO(" Instance %d\n", boot_context->boot_interface_instance); 218 } 219 } 220 221 #if STM32MP_SDMMC || STM32MP_EMMC 222 static void boot_mmc(enum mmc_device_type mmc_dev_type, 223 uint16_t boot_interface_instance) 224 { 225 int io_result __unused; 226 struct stm32_sdmmc2_params params; 227 228 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 229 230 mmc_info.mmc_dev_type = mmc_dev_type; 231 232 switch (boot_interface_instance) { 233 case 1: 234 params.reg_base = STM32MP_SDMMC1_BASE; 235 break; 236 case 2: 237 params.reg_base = STM32MP_SDMMC2_BASE; 238 break; 239 case 3: 240 params.reg_base = STM32MP_SDMMC3_BASE; 241 break; 242 default: 243 WARN("SDMMC instance not found, using default\n"); 244 if (mmc_dev_type == MMC_IS_SD) { 245 params.reg_base = STM32MP_SDMMC1_BASE; 246 } else { 247 params.reg_base = STM32MP_SDMMC2_BASE; 248 } 249 break; 250 } 251 252 if (mmc_dev_type != MMC_IS_EMMC) { 253 params.flags = MMC_FLAG_SD_CMD6; 254 } 255 256 params.device_info = &mmc_info; 257 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 258 ERROR("SDMMC%u init failed\n", boot_interface_instance); 259 panic(); 260 } 261 262 /* Open MMC as a block device to read FIP */ 263 io_result = register_io_dev_block(&mmc_dev_con); 264 if (io_result != 0) { 265 panic(); 266 } 267 268 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 269 &storage_dev_handle); 270 assert(io_result == 0); 271 272 #if STM32MP_EMMC_BOOT 273 if (mmc_dev_type == MMC_IS_EMMC) { 274 io_result = mmc_part_switch_current_boot(); 275 assert(io_result == 0); 276 277 if (get_boot_part_fip_header() != TOC_HEADER_NAME) { 278 WARN("%s: Can't find FIP header on eMMC boot partition. Trying GPT\n", 279 __func__); 280 io_result = mmc_part_switch_user(); 281 assert(io_result == 0); 282 return; 283 } 284 285 VERBOSE("%s: FIP header found on eMMC boot partition\n", 286 __func__); 287 image_block_spec.offset = STM32MP_EMMC_BOOT_FIP_OFFSET; 288 image_block_spec.length = mmc_boot_part_size() - STM32MP_EMMC_BOOT_FIP_OFFSET; 289 } 290 #endif 291 } 292 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 293 294 #if STM32MP_SPI_NOR 295 static void boot_spi_nor(boot_api_context_t *boot_context) 296 { 297 int io_result __unused; 298 299 io_result = stm32_qspi_init(); 300 assert(io_result == 0); 301 302 io_result = register_io_dev_mtd(&spi_dev_con); 303 assert(io_result == 0); 304 305 /* Open connections to device */ 306 io_result = io_dev_open(spi_dev_con, 307 (uintptr_t)&spi_nor_dev_spec, 308 &storage_dev_handle); 309 assert(io_result == 0); 310 } 311 #endif /* STM32MP_SPI_NOR */ 312 313 #if STM32MP_RAW_NAND 314 static void boot_fmc2_nand(boot_api_context_t *boot_context) 315 { 316 int io_result __unused; 317 318 io_result = stm32_fmc2_init(); 319 assert(io_result == 0); 320 321 /* Register the IO device on this platform */ 322 io_result = register_io_dev_mtd(&nand_dev_con); 323 assert(io_result == 0); 324 325 /* Open connections to device */ 326 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 327 &storage_dev_handle); 328 assert(io_result == 0); 329 } 330 #endif /* STM32MP_RAW_NAND */ 331 332 #if STM32MP_SPI_NAND 333 static void boot_spi_nand(boot_api_context_t *boot_context) 334 { 335 int io_result __unused; 336 337 io_result = stm32_qspi_init(); 338 assert(io_result == 0); 339 340 io_result = register_io_dev_mtd(&spi_dev_con); 341 assert(io_result == 0); 342 343 /* Open connections to device */ 344 io_result = io_dev_open(spi_dev_con, 345 (uintptr_t)&spi_nand_dev_spec, 346 &storage_dev_handle); 347 assert(io_result == 0); 348 } 349 #endif /* STM32MP_SPI_NAND */ 350 351 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 352 static void mmap_io_setup(void) 353 { 354 int io_result __unused; 355 356 io_result = register_io_dev_memmap(&memmap_dev_con); 357 assert(io_result == 0); 358 359 io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, 360 &storage_dev_handle); 361 assert(io_result == 0); 362 } 363 364 #if STM32MP_UART_PROGRAMMER 365 static void stm32cubeprogrammer_uart(void) 366 { 367 int ret __unused; 368 boot_api_context_t *boot_context = 369 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 370 uintptr_t uart_base; 371 372 uart_base = get_uart_address(boot_context->boot_interface_instance); 373 ret = stm32cubeprog_uart_load(uart_base, DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 374 assert(ret == 0); 375 } 376 #endif 377 378 #if STM32MP_USB_PROGRAMMER 379 static void stm32cubeprogrammer_usb(void) 380 { 381 int ret __unused; 382 struct usb_handle *pdev; 383 384 /* Init USB on platform */ 385 pdev = usb_dfu_plat_init(); 386 387 ret = stm32cubeprog_usb_load(pdev, DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 388 assert(ret == 0); 389 } 390 #endif 391 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 392 393 394 void stm32mp_io_setup(void) 395 { 396 int io_result __unused; 397 boot_api_context_t *boot_context = 398 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 399 400 print_boot_device(boot_context); 401 402 if ((boot_context->boot_partition_used_toboot == 1U) || 403 (boot_context->boot_partition_used_toboot == 2U)) { 404 INFO("Boot used partition fsbl%u\n", 405 boot_context->boot_partition_used_toboot); 406 } 407 408 io_result = register_io_dev_fip(&fip_dev_con); 409 assert(io_result == 0); 410 411 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, 412 &fip_dev_handle); 413 414 #ifndef DECRYPTION_SUPPORT_none 415 io_result = register_io_dev_enc(&enc_dev_con); 416 assert(io_result == 0); 417 418 io_result = io_dev_open(enc_dev_con, (uintptr_t)NULL, 419 &enc_dev_handle); 420 assert(io_result == 0); 421 #endif 422 423 switch (boot_context->boot_interface_selected) { 424 #if STM32MP_SDMMC 425 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 426 dmbsy(); 427 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 428 break; 429 #endif 430 #if STM32MP_EMMC 431 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 432 dmbsy(); 433 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 434 break; 435 #endif 436 #if STM32MP_SPI_NOR 437 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 438 dmbsy(); 439 boot_spi_nor(boot_context); 440 break; 441 #endif 442 #if STM32MP_RAW_NAND 443 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 444 dmbsy(); 445 boot_fmc2_nand(boot_context); 446 break; 447 #endif 448 #if STM32MP_SPI_NAND 449 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 450 dmbsy(); 451 boot_spi_nand(boot_context); 452 break; 453 #endif 454 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 455 #if STM32MP_UART_PROGRAMMER 456 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 457 #endif 458 #if STM32MP_USB_PROGRAMMER 459 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 460 #endif 461 dmbsy(); 462 mmap_io_setup(); 463 break; 464 #endif 465 466 default: 467 ERROR("Boot interface %d not supported\n", 468 boot_context->boot_interface_selected); 469 panic(); 470 break; 471 } 472 } 473 474 int bl2_plat_handle_pre_image_load(unsigned int image_id) 475 { 476 static bool gpt_init_done __unused; 477 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 478 479 switch (boot_itf) { 480 #if STM32MP_SDMMC || STM32MP_EMMC 481 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 482 #if STM32MP_EMMC_BOOT 483 if (image_block_spec.offset == STM32MP_EMMC_BOOT_FIP_OFFSET) { 484 break; 485 } 486 #endif 487 /* fallthrough */ 488 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 489 if (!gpt_init_done) { 490 /* 491 * With FWU Multi Bank feature enabled, the selection of 492 * the image to boot will be done by fwu_init calling the 493 * platform hook, plat_fwu_set_images_source. 494 */ 495 #if !PSA_FWU_SUPPORT 496 const partition_entry_t *entry; 497 const struct efi_guid img_type_guid = STM32MP_FIP_GUID; 498 uuid_t img_type_uuid; 499 500 guidcpy(&img_type_uuid, &img_type_guid); 501 partition_init(GPT_IMAGE_ID); 502 entry = get_partition_entry_by_type(&img_type_uuid); 503 if (entry == NULL) { 504 entry = get_partition_entry(FIP_IMAGE_NAME); 505 if (entry == NULL) { 506 ERROR("Could NOT find the %s partition!\n", 507 FIP_IMAGE_NAME); 508 509 return -ENOENT; 510 } 511 } 512 513 image_block_spec.offset = entry->start; 514 image_block_spec.length = entry->length; 515 #endif 516 gpt_init_done = true; 517 } else { 518 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 519 assert(bl_mem_params != NULL); 520 521 mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base; 522 mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size; 523 } 524 525 break; 526 #endif 527 528 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 529 #if STM32MP_RAW_NAND 530 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 531 #endif 532 #if STM32MP_SPI_NAND 533 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 534 #endif 535 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET; 536 break; 537 #endif 538 539 #if STM32MP_SPI_NOR 540 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 541 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET; 542 break; 543 #endif 544 545 #if STM32MP_UART_PROGRAMMER 546 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 547 if (image_id == FW_CONFIG_ID) { 548 stm32cubeprogrammer_uart(); 549 /* FIP loaded at DWL address */ 550 image_block_spec.offset = DWL_BUFFER_BASE; 551 image_block_spec.length = DWL_BUFFER_SIZE; 552 } 553 break; 554 #endif 555 #if STM32MP_USB_PROGRAMMER 556 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 557 if (image_id == FW_CONFIG_ID) { 558 stm32cubeprogrammer_usb(); 559 /* FIP loaded at DWL address */ 560 image_block_spec.offset = DWL_BUFFER_BASE; 561 image_block_spec.length = DWL_BUFFER_SIZE; 562 } 563 break; 564 #endif 565 566 default: 567 ERROR("FIP Not found\n"); 568 panic(); 569 } 570 571 return 0; 572 } 573 574 /* 575 * Return an IO device handle and specification which can be used to access 576 * an image. Use this to enforce platform load policy. 577 */ 578 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 579 uintptr_t *image_spec) 580 { 581 int rc; 582 const struct plat_io_policy *policy; 583 584 policy = FCONF_GET_PROPERTY(stm32mp, io_policies, image_id); 585 rc = policy->check(policy->image_spec); 586 if (rc == 0) { 587 *image_spec = policy->image_spec; 588 *dev_handle = *(policy->dev_handle); 589 } 590 591 return rc; 592 } 593 594 #if (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT 595 /* 596 * In each boot in non-trial mode, we set the BKP register to 597 * FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata. 598 * 599 * As long as the update agent didn't update the "accepted" field in metadata 600 * (i.e. we are in trial mode), we select the new active_index. 601 * To avoid infinite boot loop at trial boot we decrement a BKP register. 602 * If this counter is 0: 603 * - an unexpected TAMPER event raised (that resets the BKP registers to 0) 604 * - a power-off occurs before the update agent was able to update the 605 * "accepted' field 606 * - we already boot FWU_MAX_TRIAL_REBOOT times in trial mode. 607 * we select the previous_active_index. 608 */ 609 #define INVALID_BOOT_IDX 0xFFFFFFFFU 610 611 uint32_t plat_fwu_get_boot_idx(void) 612 { 613 /* 614 * Select boot index and update boot counter only once per boot 615 * even if this function is called several times. 616 */ 617 static uint32_t boot_idx = INVALID_BOOT_IDX; 618 const struct fwu_metadata *data; 619 620 data = fwu_get_metadata(); 621 622 if (boot_idx == INVALID_BOOT_IDX) { 623 boot_idx = data->active_index; 624 if (fwu_is_trial_run_state()) { 625 if (stm32_get_and_dec_fwu_trial_boot_cnt() == 0U) { 626 WARN("Trial FWU fails %u times\n", 627 FWU_MAX_TRIAL_REBOOT); 628 boot_idx = data->previous_active_index; 629 } 630 } else { 631 stm32_set_max_fwu_trial_boot_cnt(); 632 } 633 } 634 635 return boot_idx; 636 } 637 638 static void *stm32_get_image_spec(const uuid_t *img_type_uuid) 639 { 640 unsigned int i; 641 642 for (i = 0U; i < MAX_NUMBER_IDS; i++) { 643 if ((guidcmp(&policies[i].img_type_guid, img_type_uuid)) == 0) { 644 return (void *)policies[i].image_spec; 645 } 646 } 647 648 return NULL; 649 } 650 651 void plat_fwu_set_images_source(const struct fwu_metadata *metadata) 652 { 653 unsigned int i; 654 uint32_t boot_idx; 655 const partition_entry_t *entry; 656 const uuid_t *img_type_uuid, *img_uuid; 657 io_block_spec_t *image_spec; 658 659 boot_idx = plat_fwu_get_boot_idx(); 660 assert(boot_idx < NR_OF_FW_BANKS); 661 662 for (i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) { 663 img_type_uuid = &metadata->img_entry[i].img_type_uuid; 664 image_spec = stm32_get_image_spec(img_type_uuid); 665 if (image_spec == NULL) { 666 ERROR("Unable to get image spec for the image in the metadata\n"); 667 panic(); 668 } 669 670 img_uuid = 671 &metadata->img_entry[i].img_props[boot_idx].img_uuid; 672 673 entry = get_partition_entry_by_uuid(img_uuid); 674 if (entry == NULL) { 675 ERROR("Unable to find the partition with the uuid mentioned in metadata\n"); 676 panic(); 677 } 678 679 image_spec->offset = entry->start; 680 image_spec->length = entry->length; 681 } 682 } 683 684 static int plat_set_image_source(unsigned int image_id, 685 uintptr_t *handle, 686 uintptr_t *image_spec, 687 const char *part_name) 688 { 689 struct plat_io_policy *policy; 690 io_block_spec_t *spec; 691 const partition_entry_t *entry = get_partition_entry(part_name); 692 693 if (entry == NULL) { 694 ERROR("Unable to find the %s partition\n", part_name); 695 return -ENOENT; 696 } 697 698 policy = &policies[image_id]; 699 700 spec = (io_block_spec_t *)policy->image_spec; 701 spec->offset = entry->start; 702 spec->length = entry->length; 703 704 *image_spec = policy->image_spec; 705 *handle = *policy->dev_handle; 706 707 return 0; 708 } 709 710 int plat_fwu_set_metadata_image_source(unsigned int image_id, 711 uintptr_t *handle, 712 uintptr_t *image_spec) 713 { 714 char *part_name; 715 716 assert((image_id == FWU_METADATA_IMAGE_ID) || 717 (image_id == BKUP_FWU_METADATA_IMAGE_ID)); 718 719 partition_init(GPT_IMAGE_ID); 720 721 if (image_id == FWU_METADATA_IMAGE_ID) { 722 part_name = METADATA_PART_1; 723 } else { 724 part_name = METADATA_PART_2; 725 } 726 727 return plat_set_image_source(image_id, handle, image_spec, 728 part_name); 729 } 730 #endif /* (STM32MP_SDMMC || STM32MP_EMMC) && PSA_FWU_SUPPORT */ 731