1 /* 2 * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/clk.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/st/stm32mp_clkfunc.h> 20 #include <drivers/st/stm32mp1_clk.h> 21 #include <drivers/st/stm32mp1_rcc.h> 22 #include <dt-bindings/clock/stm32mp1-clksrc.h> 23 #include <lib/mmio.h> 24 #include <lib/spinlock.h> 25 #include <lib/utils_def.h> 26 #include <libfdt.h> 27 #include <plat/common/platform.h> 28 29 #include <platform_def.h> 30 31 #define MAX_HSI_HZ 64000000 32 #define USB_PHY_48_MHZ 48000000 33 34 #define TIMEOUT_US_200MS U(200000) 35 #define TIMEOUT_US_1S U(1000000) 36 37 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 38 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 39 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 40 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 41 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 42 43 const char *stm32mp_osc_node_label[NB_OSC] = { 44 [_LSI] = "clk-lsi", 45 [_LSE] = "clk-lse", 46 [_HSI] = "clk-hsi", 47 [_HSE] = "clk-hse", 48 [_CSI] = "clk-csi", 49 [_I2S_CKIN] = "i2s_ckin", 50 }; 51 52 enum stm32mp1_parent_id { 53 /* Oscillators are defined in enum stm32mp_osc_id */ 54 55 /* Other parent source */ 56 _HSI_KER = NB_OSC, 57 _HSE_KER, 58 _HSE_KER_DIV2, 59 _HSE_RTC, 60 _CSI_KER, 61 _PLL1_P, 62 _PLL1_Q, 63 _PLL1_R, 64 _PLL2_P, 65 _PLL2_Q, 66 _PLL2_R, 67 _PLL3_P, 68 _PLL3_Q, 69 _PLL3_R, 70 _PLL4_P, 71 _PLL4_Q, 72 _PLL4_R, 73 _ACLK, 74 _PCLK1, 75 _PCLK2, 76 _PCLK3, 77 _PCLK4, 78 _PCLK5, 79 _HCLK6, 80 _HCLK2, 81 _CK_PER, 82 _CK_MPU, 83 _CK_MCU, 84 _USB_PHY_48, 85 _PARENT_NB, 86 _UNKNOWN_ID = 0xff, 87 }; 88 89 /* Lists only the parent clock we are interested in */ 90 enum stm32mp1_parent_sel { 91 _I2C12_SEL, 92 _I2C35_SEL, 93 _STGEN_SEL, 94 _I2C46_SEL, 95 _SPI6_SEL, 96 _UART1_SEL, 97 _RNG1_SEL, 98 _UART6_SEL, 99 _UART24_SEL, 100 _UART35_SEL, 101 _UART78_SEL, 102 _SDMMC12_SEL, 103 _SDMMC3_SEL, 104 _QSPI_SEL, 105 _FMC_SEL, 106 _AXIS_SEL, 107 _MCUS_SEL, 108 _USBPHY_SEL, 109 _USBO_SEL, 110 _MPU_SEL, 111 _CKPER_SEL, 112 _RTC_SEL, 113 _PARENT_SEL_NB, 114 _UNKNOWN_SEL = 0xff, 115 }; 116 117 /* State the parent clock ID straight related to a clock */ 118 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 119 [_HSE] = CK_HSE, 120 [_HSI] = CK_HSI, 121 [_CSI] = CK_CSI, 122 [_LSE] = CK_LSE, 123 [_LSI] = CK_LSI, 124 [_I2S_CKIN] = _UNKNOWN_ID, 125 [_USB_PHY_48] = _UNKNOWN_ID, 126 [_HSI_KER] = CK_HSI, 127 [_HSE_KER] = CK_HSE, 128 [_HSE_KER_DIV2] = CK_HSE_DIV2, 129 [_HSE_RTC] = _UNKNOWN_ID, 130 [_CSI_KER] = CK_CSI, 131 [_PLL1_P] = PLL1_P, 132 [_PLL1_Q] = PLL1_Q, 133 [_PLL1_R] = PLL1_R, 134 [_PLL2_P] = PLL2_P, 135 [_PLL2_Q] = PLL2_Q, 136 [_PLL2_R] = PLL2_R, 137 [_PLL3_P] = PLL3_P, 138 [_PLL3_Q] = PLL3_Q, 139 [_PLL3_R] = PLL3_R, 140 [_PLL4_P] = PLL4_P, 141 [_PLL4_Q] = PLL4_Q, 142 [_PLL4_R] = PLL4_R, 143 [_ACLK] = CK_AXI, 144 [_PCLK1] = CK_AXI, 145 [_PCLK2] = CK_AXI, 146 [_PCLK3] = CK_AXI, 147 [_PCLK4] = CK_AXI, 148 [_PCLK5] = CK_AXI, 149 [_CK_PER] = CK_PER, 150 [_CK_MPU] = CK_MPU, 151 [_CK_MCU] = CK_MCU, 152 }; 153 154 static unsigned int clock_id2parent_id(unsigned long id) 155 { 156 unsigned int n; 157 158 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 159 if (parent_id_clock_id[n] == id) { 160 return n; 161 } 162 } 163 164 return _UNKNOWN_ID; 165 } 166 167 enum stm32mp1_pll_id { 168 _PLL1, 169 _PLL2, 170 _PLL3, 171 _PLL4, 172 _PLL_NB 173 }; 174 175 enum stm32mp1_div_id { 176 _DIV_P, 177 _DIV_Q, 178 _DIV_R, 179 _DIV_NB, 180 }; 181 182 enum stm32mp1_clksrc_id { 183 CLKSRC_MPU, 184 CLKSRC_AXI, 185 CLKSRC_MCU, 186 CLKSRC_PLL12, 187 CLKSRC_PLL3, 188 CLKSRC_PLL4, 189 CLKSRC_RTC, 190 CLKSRC_MCO1, 191 CLKSRC_MCO2, 192 CLKSRC_NB 193 }; 194 195 enum stm32mp1_clkdiv_id { 196 CLKDIV_MPU, 197 CLKDIV_AXI, 198 CLKDIV_MCU, 199 CLKDIV_APB1, 200 CLKDIV_APB2, 201 CLKDIV_APB3, 202 CLKDIV_APB4, 203 CLKDIV_APB5, 204 CLKDIV_RTC, 205 CLKDIV_MCO1, 206 CLKDIV_MCO2, 207 CLKDIV_NB 208 }; 209 210 enum stm32mp1_pllcfg { 211 PLLCFG_M, 212 PLLCFG_N, 213 PLLCFG_P, 214 PLLCFG_Q, 215 PLLCFG_R, 216 PLLCFG_O, 217 PLLCFG_NB 218 }; 219 220 enum stm32mp1_pllcsg { 221 PLLCSG_MOD_PER, 222 PLLCSG_INC_STEP, 223 PLLCSG_SSCG_MODE, 224 PLLCSG_NB 225 }; 226 227 enum stm32mp1_plltype { 228 PLL_800, 229 PLL_1600, 230 PLL_TYPE_NB 231 }; 232 233 struct stm32mp1_pll { 234 uint8_t refclk_min; 235 uint8_t refclk_max; 236 uint8_t divn_max; 237 }; 238 239 struct stm32mp1_clk_gate { 240 uint16_t offset; 241 uint8_t bit; 242 uint8_t index; 243 uint8_t set_clr; 244 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 245 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 246 }; 247 248 struct stm32mp1_clk_sel { 249 uint16_t offset; 250 uint8_t src; 251 uint8_t msk; 252 uint8_t nb_parent; 253 const uint8_t *parent; 254 }; 255 256 #define REFCLK_SIZE 4 257 struct stm32mp1_clk_pll { 258 enum stm32mp1_plltype plltype; 259 uint16_t rckxselr; 260 uint16_t pllxcfgr1; 261 uint16_t pllxcfgr2; 262 uint16_t pllxfracr; 263 uint16_t pllxcr; 264 uint16_t pllxcsgr; 265 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 266 }; 267 268 /* Clocks with selectable source and non set/clr register access */ 269 #define _CLK_SELEC(off, b, idx, s) \ 270 { \ 271 .offset = (off), \ 272 .bit = (b), \ 273 .index = (idx), \ 274 .set_clr = 0, \ 275 .sel = (s), \ 276 .fixed = _UNKNOWN_ID, \ 277 } 278 279 /* Clocks with fixed source and non set/clr register access */ 280 #define _CLK_FIXED(off, b, idx, f) \ 281 { \ 282 .offset = (off), \ 283 .bit = (b), \ 284 .index = (idx), \ 285 .set_clr = 0, \ 286 .sel = _UNKNOWN_SEL, \ 287 .fixed = (f), \ 288 } 289 290 /* Clocks with selectable source and set/clr register access */ 291 #define _CLK_SC_SELEC(off, b, idx, s) \ 292 { \ 293 .offset = (off), \ 294 .bit = (b), \ 295 .index = (idx), \ 296 .set_clr = 1, \ 297 .sel = (s), \ 298 .fixed = _UNKNOWN_ID, \ 299 } 300 301 /* Clocks with fixed source and set/clr register access */ 302 #define _CLK_SC_FIXED(off, b, idx, f) \ 303 { \ 304 .offset = (off), \ 305 .bit = (b), \ 306 .index = (idx), \ 307 .set_clr = 1, \ 308 .sel = _UNKNOWN_SEL, \ 309 .fixed = (f), \ 310 } 311 312 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 313 [_ ## _label ## _SEL] = { \ 314 .offset = _rcc_selr, \ 315 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 316 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 317 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 318 .parent = (_parents), \ 319 .nb_parent = ARRAY_SIZE(_parents) \ 320 } 321 322 #define _CLK_PLL(idx, type, off1, off2, off3, \ 323 off4, off5, off6, \ 324 p1, p2, p3, p4) \ 325 [(idx)] = { \ 326 .plltype = (type), \ 327 .rckxselr = (off1), \ 328 .pllxcfgr1 = (off2), \ 329 .pllxcfgr2 = (off3), \ 330 .pllxfracr = (off4), \ 331 .pllxcr = (off5), \ 332 .pllxcsgr = (off6), \ 333 .refclk[0] = (p1), \ 334 .refclk[1] = (p2), \ 335 .refclk[2] = (p3), \ 336 .refclk[3] = (p4), \ 337 } 338 339 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 340 341 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 342 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), 343 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 344 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), 345 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 346 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 347 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 348 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 349 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 350 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), 351 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 352 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 353 354 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 355 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 356 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 357 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 358 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 359 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 360 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 361 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 362 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 363 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 364 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 365 366 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 367 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 368 369 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 370 371 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 372 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 373 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 374 375 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 376 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 377 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 378 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 379 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 380 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 381 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 382 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 383 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 384 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 385 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 386 387 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 388 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 389 390 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 391 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 392 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 393 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 394 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 395 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 396 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 397 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 398 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 399 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 400 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 401 402 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 403 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 404 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 405 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 406 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 407 408 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 409 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 410 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 411 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 412 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 413 414 _CLK_SELEC(RCC_BDCR, 20, RTC, _RTC_SEL), 415 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 416 }; 417 418 static const uint8_t i2c12_parents[] = { 419 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 420 }; 421 422 static const uint8_t i2c35_parents[] = { 423 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 424 }; 425 426 static const uint8_t stgen_parents[] = { 427 _HSI_KER, _HSE_KER 428 }; 429 430 static const uint8_t i2c46_parents[] = { 431 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 432 }; 433 434 static const uint8_t spi6_parents[] = { 435 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 436 }; 437 438 static const uint8_t usart1_parents[] = { 439 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 440 }; 441 442 static const uint8_t rng1_parents[] = { 443 _CSI, _PLL4_R, _LSE, _LSI 444 }; 445 446 static const uint8_t uart6_parents[] = { 447 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 448 }; 449 450 static const uint8_t uart234578_parents[] = { 451 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 452 }; 453 454 static const uint8_t sdmmc12_parents[] = { 455 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 456 }; 457 458 static const uint8_t sdmmc3_parents[] = { 459 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 460 }; 461 462 static const uint8_t qspi_parents[] = { 463 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 464 }; 465 466 static const uint8_t fmc_parents[] = { 467 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 468 }; 469 470 static const uint8_t axiss_parents[] = { 471 _HSI, _HSE, _PLL2_P 472 }; 473 474 static const uint8_t mcuss_parents[] = { 475 _HSI, _HSE, _CSI, _PLL3_P 476 }; 477 478 static const uint8_t usbphy_parents[] = { 479 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 480 }; 481 482 static const uint8_t usbo_parents[] = { 483 _PLL4_R, _USB_PHY_48 484 }; 485 486 static const uint8_t mpu_parents[] = { 487 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 488 }; 489 490 static const uint8_t per_parents[] = { 491 _HSI, _HSE, _CSI, 492 }; 493 494 static const uint8_t rtc_parents[] = { 495 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 496 }; 497 498 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 499 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 500 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 501 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 502 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 503 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 504 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 505 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 506 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 507 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 508 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 509 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 510 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 511 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 512 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 513 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 514 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 515 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 516 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 517 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 518 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 519 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 520 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 521 }; 522 523 /* Define characteristic of PLL according type */ 524 #define DIVN_MIN 24 525 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 526 [PLL_800] = { 527 .refclk_min = 4, 528 .refclk_max = 16, 529 .divn_max = 99, 530 }, 531 [PLL_1600] = { 532 .refclk_min = 8, 533 .refclk_max = 16, 534 .divn_max = 199, 535 }, 536 }; 537 538 /* PLLNCFGR2 register divider by output */ 539 static const uint8_t pllncfgr2[_DIV_NB] = { 540 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 541 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 542 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 543 }; 544 545 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 546 _CLK_PLL(_PLL1, PLL_1600, 547 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 548 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 549 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 550 _CLK_PLL(_PLL2, PLL_1600, 551 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 552 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 553 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 554 _CLK_PLL(_PLL3, PLL_800, 555 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 556 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 557 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 558 _CLK_PLL(_PLL4, PLL_800, 559 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 560 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 561 _HSI, _HSE, _CSI, _I2S_CKIN), 562 }; 563 564 /* Prescaler table lookups for clock computation */ 565 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 566 static const uint8_t stm32mp1_mcu_div[16] = { 567 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 568 }; 569 570 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 571 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 572 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 573 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 574 0, 1, 2, 3, 4, 4, 4, 4 575 }; 576 577 /* div = /1 /2 /3 /4 */ 578 static const uint8_t stm32mp1_axi_div[8] = { 579 1, 2, 3, 4, 4, 4, 4, 4 580 }; 581 582 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 583 [_HSI] = "HSI", 584 [_HSE] = "HSE", 585 [_CSI] = "CSI", 586 [_LSI] = "LSI", 587 [_LSE] = "LSE", 588 [_I2S_CKIN] = "I2S_CKIN", 589 [_HSI_KER] = "HSI_KER", 590 [_HSE_KER] = "HSE_KER", 591 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 592 [_HSE_RTC] = "HSE_RTC", 593 [_CSI_KER] = "CSI_KER", 594 [_PLL1_P] = "PLL1_P", 595 [_PLL1_Q] = "PLL1_Q", 596 [_PLL1_R] = "PLL1_R", 597 [_PLL2_P] = "PLL2_P", 598 [_PLL2_Q] = "PLL2_Q", 599 [_PLL2_R] = "PLL2_R", 600 [_PLL3_P] = "PLL3_P", 601 [_PLL3_Q] = "PLL3_Q", 602 [_PLL3_R] = "PLL3_R", 603 [_PLL4_P] = "PLL4_P", 604 [_PLL4_Q] = "PLL4_Q", 605 [_PLL4_R] = "PLL4_R", 606 [_ACLK] = "ACLK", 607 [_PCLK1] = "PCLK1", 608 [_PCLK2] = "PCLK2", 609 [_PCLK3] = "PCLK3", 610 [_PCLK4] = "PCLK4", 611 [_PCLK5] = "PCLK5", 612 [_HCLK6] = "KCLK6", 613 [_HCLK2] = "HCLK2", 614 [_CK_PER] = "CK_PER", 615 [_CK_MPU] = "CK_MPU", 616 [_CK_MCU] = "CK_MCU", 617 [_USB_PHY_48] = "USB_PHY_48", 618 }; 619 620 /* RCC clock device driver private */ 621 static unsigned long stm32mp1_osc[NB_OSC]; 622 static struct spinlock reg_lock; 623 static unsigned int gate_refcounts[NB_GATES]; 624 static struct spinlock refcount_lock; 625 626 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 627 { 628 return &stm32mp1_clk_gate[idx]; 629 } 630 631 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 632 { 633 return &stm32mp1_clk_sel[idx]; 634 } 635 636 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 637 { 638 return &stm32mp1_clk_pll[idx]; 639 } 640 641 static void stm32mp1_clk_lock(struct spinlock *lock) 642 { 643 if (stm32mp_lock_available()) { 644 /* Assume interrupts are masked */ 645 spin_lock(lock); 646 } 647 } 648 649 static void stm32mp1_clk_unlock(struct spinlock *lock) 650 { 651 if (stm32mp_lock_available()) { 652 spin_unlock(lock); 653 } 654 } 655 656 bool stm32mp1_rcc_is_secure(void) 657 { 658 uintptr_t rcc_base = stm32mp_rcc_base(); 659 uint32_t mask = RCC_TZCR_TZEN; 660 661 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 662 } 663 664 bool stm32mp1_rcc_is_mckprot(void) 665 { 666 uintptr_t rcc_base = stm32mp_rcc_base(); 667 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 668 669 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 670 } 671 672 void stm32mp1_clk_rcc_regs_lock(void) 673 { 674 stm32mp1_clk_lock(®_lock); 675 } 676 677 void stm32mp1_clk_rcc_regs_unlock(void) 678 { 679 stm32mp1_clk_unlock(®_lock); 680 } 681 682 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 683 { 684 if (idx >= NB_OSC) { 685 return 0; 686 } 687 688 return stm32mp1_osc[idx]; 689 } 690 691 static int stm32mp1_clk_get_gated_id(unsigned long id) 692 { 693 unsigned int i; 694 695 for (i = 0U; i < NB_GATES; i++) { 696 if (gate_ref(i)->index == id) { 697 return i; 698 } 699 } 700 701 ERROR("%s: clk id %lu not found\n", __func__, id); 702 703 return -EINVAL; 704 } 705 706 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 707 { 708 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 709 } 710 711 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 712 { 713 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 714 } 715 716 static int stm32mp1_clk_get_parent(unsigned long id) 717 { 718 const struct stm32mp1_clk_sel *sel; 719 uint32_t p_sel; 720 int i; 721 enum stm32mp1_parent_id p; 722 enum stm32mp1_parent_sel s; 723 uintptr_t rcc_base = stm32mp_rcc_base(); 724 725 /* Few non gateable clock have a static parent ID, find them */ 726 i = (int)clock_id2parent_id(id); 727 if (i != _UNKNOWN_ID) { 728 return i; 729 } 730 731 i = stm32mp1_clk_get_gated_id(id); 732 if (i < 0) { 733 panic(); 734 } 735 736 p = stm32mp1_clk_get_fixed_parent(i); 737 if (p < _PARENT_NB) { 738 return (int)p; 739 } 740 741 s = stm32mp1_clk_get_sel(i); 742 if (s == _UNKNOWN_SEL) { 743 return -EINVAL; 744 } 745 if (s >= _PARENT_SEL_NB) { 746 panic(); 747 } 748 749 sel = clk_sel_ref(s); 750 p_sel = (mmio_read_32(rcc_base + sel->offset) & 751 (sel->msk << sel->src)) >> sel->src; 752 if (p_sel < sel->nb_parent) { 753 return (int)sel->parent[p_sel]; 754 } 755 756 return -EINVAL; 757 } 758 759 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 760 { 761 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 762 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 763 764 return stm32mp1_clk_get_fixed(pll->refclk[src]); 765 } 766 767 /* 768 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 769 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 770 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 771 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 772 */ 773 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 774 { 775 unsigned long refclk, fvco; 776 uint32_t cfgr1, fracr, divm, divn; 777 uintptr_t rcc_base = stm32mp_rcc_base(); 778 779 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 780 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 781 782 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 783 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 784 785 refclk = stm32mp1_pll_get_fref(pll); 786 787 /* 788 * With FRACV : 789 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 790 * Without FRACV 791 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 792 */ 793 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 794 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 795 RCC_PLLNFRACR_FRACV_SHIFT; 796 unsigned long long numerator, denominator; 797 798 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 799 numerator = refclk * numerator; 800 denominator = ((unsigned long long)divm + 1U) << 13; 801 fvco = (unsigned long)(numerator / denominator); 802 } else { 803 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 804 } 805 806 return fvco; 807 } 808 809 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 810 enum stm32mp1_div_id div_id) 811 { 812 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 813 unsigned long dfout; 814 uint32_t cfgr2, divy; 815 816 if (div_id >= _DIV_NB) { 817 return 0; 818 } 819 820 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 821 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 822 823 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 824 825 return dfout; 826 } 827 828 static unsigned long get_clock_rate(int p) 829 { 830 uint32_t reg, clkdiv; 831 unsigned long clock = 0; 832 uintptr_t rcc_base = stm32mp_rcc_base(); 833 834 switch (p) { 835 case _CK_MPU: 836 /* MPU sub system */ 837 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 838 switch (reg & RCC_SELR_SRC_MASK) { 839 case RCC_MPCKSELR_HSI: 840 clock = stm32mp1_clk_get_fixed(_HSI); 841 break; 842 case RCC_MPCKSELR_HSE: 843 clock = stm32mp1_clk_get_fixed(_HSE); 844 break; 845 case RCC_MPCKSELR_PLL: 846 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 847 break; 848 case RCC_MPCKSELR_PLL_MPUDIV: 849 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 850 851 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 852 clkdiv = reg & RCC_MPUDIV_MASK; 853 clock >>= stm32mp1_mpu_div[clkdiv]; 854 break; 855 default: 856 break; 857 } 858 break; 859 /* AXI sub system */ 860 case _ACLK: 861 case _HCLK2: 862 case _HCLK6: 863 case _PCLK4: 864 case _PCLK5: 865 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 866 switch (reg & RCC_SELR_SRC_MASK) { 867 case RCC_ASSCKSELR_HSI: 868 clock = stm32mp1_clk_get_fixed(_HSI); 869 break; 870 case RCC_ASSCKSELR_HSE: 871 clock = stm32mp1_clk_get_fixed(_HSE); 872 break; 873 case RCC_ASSCKSELR_PLL: 874 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 875 break; 876 default: 877 break; 878 } 879 880 /* System clock divider */ 881 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 882 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 883 884 switch (p) { 885 case _PCLK4: 886 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 887 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 888 break; 889 case _PCLK5: 890 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 891 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 892 break; 893 default: 894 break; 895 } 896 break; 897 /* MCU sub system */ 898 case _CK_MCU: 899 case _PCLK1: 900 case _PCLK2: 901 case _PCLK3: 902 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 903 switch (reg & RCC_SELR_SRC_MASK) { 904 case RCC_MSSCKSELR_HSI: 905 clock = stm32mp1_clk_get_fixed(_HSI); 906 break; 907 case RCC_MSSCKSELR_HSE: 908 clock = stm32mp1_clk_get_fixed(_HSE); 909 break; 910 case RCC_MSSCKSELR_CSI: 911 clock = stm32mp1_clk_get_fixed(_CSI); 912 break; 913 case RCC_MSSCKSELR_PLL: 914 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 915 break; 916 default: 917 break; 918 } 919 920 /* MCU clock divider */ 921 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 922 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 923 924 switch (p) { 925 case _PCLK1: 926 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 927 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 928 break; 929 case _PCLK2: 930 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 931 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 932 break; 933 case _PCLK3: 934 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 935 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 936 break; 937 case _CK_MCU: 938 default: 939 break; 940 } 941 break; 942 case _CK_PER: 943 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 944 switch (reg & RCC_SELR_SRC_MASK) { 945 case RCC_CPERCKSELR_HSI: 946 clock = stm32mp1_clk_get_fixed(_HSI); 947 break; 948 case RCC_CPERCKSELR_HSE: 949 clock = stm32mp1_clk_get_fixed(_HSE); 950 break; 951 case RCC_CPERCKSELR_CSI: 952 clock = stm32mp1_clk_get_fixed(_CSI); 953 break; 954 default: 955 break; 956 } 957 break; 958 case _HSI: 959 case _HSI_KER: 960 clock = stm32mp1_clk_get_fixed(_HSI); 961 break; 962 case _CSI: 963 case _CSI_KER: 964 clock = stm32mp1_clk_get_fixed(_CSI); 965 break; 966 case _HSE: 967 case _HSE_KER: 968 clock = stm32mp1_clk_get_fixed(_HSE); 969 break; 970 case _HSE_KER_DIV2: 971 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 972 break; 973 case _HSE_RTC: 974 clock = stm32mp1_clk_get_fixed(_HSE); 975 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 976 break; 977 case _LSI: 978 clock = stm32mp1_clk_get_fixed(_LSI); 979 break; 980 case _LSE: 981 clock = stm32mp1_clk_get_fixed(_LSE); 982 break; 983 /* PLL */ 984 case _PLL1_P: 985 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 986 break; 987 case _PLL1_Q: 988 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 989 break; 990 case _PLL1_R: 991 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 992 break; 993 case _PLL2_P: 994 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 995 break; 996 case _PLL2_Q: 997 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 998 break; 999 case _PLL2_R: 1000 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1001 break; 1002 case _PLL3_P: 1003 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1004 break; 1005 case _PLL3_Q: 1006 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1007 break; 1008 case _PLL3_R: 1009 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1010 break; 1011 case _PLL4_P: 1012 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1013 break; 1014 case _PLL4_Q: 1015 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1016 break; 1017 case _PLL4_R: 1018 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1019 break; 1020 /* Other */ 1021 case _USB_PHY_48: 1022 clock = USB_PHY_48_MHZ; 1023 break; 1024 default: 1025 break; 1026 } 1027 1028 return clock; 1029 } 1030 1031 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1032 { 1033 uintptr_t rcc_base = stm32mp_rcc_base(); 1034 1035 VERBOSE("Enable clock %u\n", gate->index); 1036 1037 if (gate->set_clr != 0U) { 1038 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1039 } else { 1040 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1041 } 1042 } 1043 1044 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1045 { 1046 uintptr_t rcc_base = stm32mp_rcc_base(); 1047 1048 VERBOSE("Disable clock %u\n", gate->index); 1049 1050 if (gate->set_clr != 0U) { 1051 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1052 BIT(gate->bit)); 1053 } else { 1054 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1055 } 1056 } 1057 1058 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1059 { 1060 uintptr_t rcc_base = stm32mp_rcc_base(); 1061 1062 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1063 } 1064 1065 unsigned int stm32mp1_clk_get_refcount(unsigned long id) 1066 { 1067 int i = stm32mp1_clk_get_gated_id(id); 1068 1069 if (i < 0) { 1070 panic(); 1071 } 1072 1073 return gate_refcounts[i]; 1074 } 1075 1076 /* Oscillators and PLLs are not gated at runtime */ 1077 static bool clock_is_always_on(unsigned long id) 1078 { 1079 switch (id) { 1080 case CK_HSE: 1081 case CK_CSI: 1082 case CK_LSI: 1083 case CK_LSE: 1084 case CK_HSI: 1085 case CK_HSE_DIV2: 1086 case PLL1_Q: 1087 case PLL1_R: 1088 case PLL2_P: 1089 case PLL2_Q: 1090 case PLL2_R: 1091 case PLL3_P: 1092 case PLL3_Q: 1093 case PLL3_R: 1094 case CK_AXI: 1095 case CK_MPU: 1096 case CK_MCU: 1097 case RTC: 1098 return true; 1099 default: 1100 return false; 1101 } 1102 } 1103 1104 void __stm32mp1_clk_enable(unsigned long id, bool secure) 1105 { 1106 const struct stm32mp1_clk_gate *gate; 1107 int i; 1108 unsigned int *refcnt; 1109 1110 if (clock_is_always_on(id)) { 1111 return; 1112 } 1113 1114 i = stm32mp1_clk_get_gated_id(id); 1115 if (i < 0) { 1116 ERROR("Clock %lu can't be enabled\n", id); 1117 panic(); 1118 } 1119 1120 gate = gate_ref(i); 1121 refcnt = &gate_refcounts[i]; 1122 1123 stm32mp1_clk_lock(&refcount_lock); 1124 1125 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { 1126 __clk_enable(gate); 1127 } 1128 1129 stm32mp1_clk_unlock(&refcount_lock); 1130 } 1131 1132 void __stm32mp1_clk_disable(unsigned long id, bool secure) 1133 { 1134 const struct stm32mp1_clk_gate *gate; 1135 int i; 1136 unsigned int *refcnt; 1137 1138 if (clock_is_always_on(id)) { 1139 return; 1140 } 1141 1142 i = stm32mp1_clk_get_gated_id(id); 1143 if (i < 0) { 1144 ERROR("Clock %lu can't be disabled\n", id); 1145 panic(); 1146 } 1147 1148 gate = gate_ref(i); 1149 refcnt = &gate_refcounts[i]; 1150 1151 stm32mp1_clk_lock(&refcount_lock); 1152 1153 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { 1154 __clk_disable(gate); 1155 } 1156 1157 stm32mp1_clk_unlock(&refcount_lock); 1158 } 1159 1160 static int stm32mp_clk_enable(unsigned long id) 1161 { 1162 __stm32mp1_clk_enable(id, true); 1163 1164 return 0; 1165 } 1166 1167 static void stm32mp_clk_disable(unsigned long id) 1168 { 1169 __stm32mp1_clk_disable(id, true); 1170 } 1171 1172 static bool stm32mp_clk_is_enabled(unsigned long id) 1173 { 1174 int i; 1175 1176 if (clock_is_always_on(id)) { 1177 return true; 1178 } 1179 1180 i = stm32mp1_clk_get_gated_id(id); 1181 if (i < 0) { 1182 panic(); 1183 } 1184 1185 return __clk_is_enabled(gate_ref(i)); 1186 } 1187 1188 static unsigned long stm32mp_clk_get_rate(unsigned long id) 1189 { 1190 uintptr_t rcc_base = stm32mp_rcc_base(); 1191 int p = stm32mp1_clk_get_parent(id); 1192 uint32_t prescaler, timpre; 1193 unsigned long parent_rate; 1194 1195 if (p < 0) { 1196 return 0; 1197 } 1198 1199 parent_rate = get_clock_rate(p); 1200 1201 switch (id) { 1202 case TIM2_K: 1203 case TIM3_K: 1204 case TIM4_K: 1205 case TIM5_K: 1206 case TIM6_K: 1207 case TIM7_K: 1208 case TIM12_K: 1209 case TIM13_K: 1210 case TIM14_K: 1211 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & 1212 RCC_APBXDIV_MASK; 1213 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & 1214 RCC_TIMGXPRER_TIMGXPRE; 1215 break; 1216 1217 case TIM1_K: 1218 case TIM8_K: 1219 case TIM15_K: 1220 case TIM16_K: 1221 case TIM17_K: 1222 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & 1223 RCC_APBXDIV_MASK; 1224 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & 1225 RCC_TIMGXPRER_TIMGXPRE; 1226 break; 1227 1228 default: 1229 return parent_rate; 1230 } 1231 1232 if (prescaler == 0U) { 1233 return parent_rate; 1234 } 1235 1236 return parent_rate * (timpre + 1U) * 2U; 1237 } 1238 1239 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1240 { 1241 uintptr_t address = stm32mp_rcc_base() + offset; 1242 1243 if (enable) { 1244 mmio_setbits_32(address, mask_on); 1245 } else { 1246 mmio_clrbits_32(address, mask_on); 1247 } 1248 } 1249 1250 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1251 { 1252 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1253 uintptr_t address = stm32mp_rcc_base() + offset; 1254 1255 mmio_write_32(address, mask_on); 1256 } 1257 1258 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1259 { 1260 uint64_t timeout; 1261 uint32_t mask_test; 1262 uintptr_t address = stm32mp_rcc_base() + offset; 1263 1264 if (enable) { 1265 mask_test = mask_rdy; 1266 } else { 1267 mask_test = 0; 1268 } 1269 1270 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1271 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1272 if (timeout_elapsed(timeout)) { 1273 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1274 mask_rdy, address, enable, mmio_read_32(address)); 1275 return -ETIMEDOUT; 1276 } 1277 } 1278 1279 return 0; 1280 } 1281 1282 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1283 { 1284 uint32_t value; 1285 uintptr_t rcc_base = stm32mp_rcc_base(); 1286 1287 if (digbyp) { 1288 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1289 } 1290 1291 if (bypass || digbyp) { 1292 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1293 } 1294 1295 /* 1296 * Warning: not recommended to switch directly from "high drive" 1297 * to "medium low drive", and vice-versa. 1298 */ 1299 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1300 RCC_BDCR_LSEDRV_SHIFT; 1301 1302 while (value != lsedrv) { 1303 if (value > lsedrv) { 1304 value--; 1305 } else { 1306 value++; 1307 } 1308 1309 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1310 RCC_BDCR_LSEDRV_MASK, 1311 value << RCC_BDCR_LSEDRV_SHIFT); 1312 } 1313 1314 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1315 } 1316 1317 static void stm32mp1_lse_wait(void) 1318 { 1319 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1320 VERBOSE("%s: failed\n", __func__); 1321 } 1322 } 1323 1324 static void stm32mp1_lsi_set(bool enable) 1325 { 1326 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1327 1328 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1329 VERBOSE("%s: failed\n", __func__); 1330 } 1331 } 1332 1333 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1334 { 1335 uintptr_t rcc_base = stm32mp_rcc_base(); 1336 1337 if (digbyp) { 1338 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1339 } 1340 1341 if (bypass || digbyp) { 1342 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1343 } 1344 1345 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1346 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1347 VERBOSE("%s: failed\n", __func__); 1348 } 1349 1350 if (css) { 1351 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1352 } 1353 1354 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 1355 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && 1356 (!(digbyp || bypass))) { 1357 panic(); 1358 } 1359 #endif 1360 } 1361 1362 static void stm32mp1_csi_set(bool enable) 1363 { 1364 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1365 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1366 VERBOSE("%s: failed\n", __func__); 1367 } 1368 } 1369 1370 static void stm32mp1_hsi_set(bool enable) 1371 { 1372 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1373 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1374 VERBOSE("%s: failed\n", __func__); 1375 } 1376 } 1377 1378 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1379 { 1380 uint64_t timeout; 1381 uintptr_t rcc_base = stm32mp_rcc_base(); 1382 uintptr_t address = rcc_base + RCC_OCRDYR; 1383 1384 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1385 RCC_HSICFGR_HSIDIV_MASK, 1386 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1387 1388 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1389 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1390 if (timeout_elapsed(timeout)) { 1391 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1392 address, mmio_read_32(address)); 1393 return -ETIMEDOUT; 1394 } 1395 } 1396 1397 return 0; 1398 } 1399 1400 static int stm32mp1_hsidiv(unsigned long hsifreq) 1401 { 1402 uint8_t hsidiv; 1403 uint32_t hsidivfreq = MAX_HSI_HZ; 1404 1405 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1406 if (hsidivfreq == hsifreq) { 1407 break; 1408 } 1409 1410 hsidivfreq /= 2U; 1411 } 1412 1413 if (hsidiv == 4U) { 1414 ERROR("Invalid clk-hsi frequency\n"); 1415 return -1; 1416 } 1417 1418 if (hsidiv != 0U) { 1419 return stm32mp1_set_hsidiv(hsidiv); 1420 } 1421 1422 return 0; 1423 } 1424 1425 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1426 unsigned int clksrc, 1427 uint32_t *pllcfg, int plloff) 1428 { 1429 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1430 uintptr_t rcc_base = stm32mp_rcc_base(); 1431 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1432 enum stm32mp1_plltype type = pll->plltype; 1433 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1434 unsigned long refclk; 1435 uint32_t ifrge = 0U; 1436 uint32_t src, value, fracv = 0; 1437 void *fdt; 1438 1439 /* Check PLL output */ 1440 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1441 return false; 1442 } 1443 1444 /* Check current clksrc */ 1445 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1446 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1447 return false; 1448 } 1449 1450 /* Check Div */ 1451 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1452 1453 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1454 (pllcfg[PLLCFG_M] + 1U); 1455 1456 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1457 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1458 return false; 1459 } 1460 1461 if ((type == PLL_800) && (refclk >= 8000000U)) { 1462 ifrge = 1U; 1463 } 1464 1465 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1466 RCC_PLLNCFGR1_DIVN_MASK; 1467 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1468 RCC_PLLNCFGR1_DIVM_MASK; 1469 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1470 RCC_PLLNCFGR1_IFRGE_MASK; 1471 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1472 return false; 1473 } 1474 1475 /* Fractional configuration */ 1476 if (fdt_get_address(&fdt) == 1) { 1477 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1478 } 1479 1480 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1481 value |= RCC_PLLNFRACR_FRACLE; 1482 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1483 return false; 1484 } 1485 1486 /* Output config */ 1487 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1488 RCC_PLLNCFGR2_DIVP_MASK; 1489 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1490 RCC_PLLNCFGR2_DIVQ_MASK; 1491 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1492 RCC_PLLNCFGR2_DIVR_MASK; 1493 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1494 return false; 1495 } 1496 1497 return true; 1498 } 1499 1500 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1501 { 1502 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1503 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1504 1505 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1506 mmio_clrsetbits_32(pllxcr, 1507 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1508 RCC_PLLNCR_DIVREN, 1509 RCC_PLLNCR_PLLON); 1510 } 1511 1512 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1513 { 1514 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1515 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1516 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1517 1518 /* Wait PLL lock */ 1519 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1520 if (timeout_elapsed(timeout)) { 1521 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1522 pll_id, pllxcr, mmio_read_32(pllxcr)); 1523 return -ETIMEDOUT; 1524 } 1525 } 1526 1527 /* Start the requested output */ 1528 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1529 1530 return 0; 1531 } 1532 1533 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1534 { 1535 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1536 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1537 uint64_t timeout; 1538 1539 /* Stop all output */ 1540 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1541 RCC_PLLNCR_DIVREN); 1542 1543 /* Stop PLL */ 1544 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1545 1546 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1547 /* Wait PLL stopped */ 1548 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1549 if (timeout_elapsed(timeout)) { 1550 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1551 pll_id, pllxcr, mmio_read_32(pllxcr)); 1552 return -ETIMEDOUT; 1553 } 1554 } 1555 1556 return 0; 1557 } 1558 1559 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1560 uint32_t *pllcfg) 1561 { 1562 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1563 uintptr_t rcc_base = stm32mp_rcc_base(); 1564 uint32_t value; 1565 1566 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1567 RCC_PLLNCFGR2_DIVP_MASK; 1568 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1569 RCC_PLLNCFGR2_DIVQ_MASK; 1570 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1571 RCC_PLLNCFGR2_DIVR_MASK; 1572 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1573 } 1574 1575 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1576 uint32_t *pllcfg, uint32_t fracv) 1577 { 1578 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1579 uintptr_t rcc_base = stm32mp_rcc_base(); 1580 enum stm32mp1_plltype type = pll->plltype; 1581 unsigned long refclk; 1582 uint32_t ifrge = 0; 1583 uint32_t src, value; 1584 1585 src = mmio_read_32(rcc_base + pll->rckxselr) & 1586 RCC_SELR_REFCLK_SRC_MASK; 1587 1588 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1589 (pllcfg[PLLCFG_M] + 1U); 1590 1591 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1592 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1593 return -EINVAL; 1594 } 1595 1596 if ((type == PLL_800) && (refclk >= 8000000U)) { 1597 ifrge = 1U; 1598 } 1599 1600 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1601 RCC_PLLNCFGR1_DIVN_MASK; 1602 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1603 RCC_PLLNCFGR1_DIVM_MASK; 1604 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1605 RCC_PLLNCFGR1_IFRGE_MASK; 1606 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1607 1608 /* Fractional configuration */ 1609 value = 0; 1610 mmio_write_32(rcc_base + pll->pllxfracr, value); 1611 1612 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1613 mmio_write_32(rcc_base + pll->pllxfracr, value); 1614 1615 value |= RCC_PLLNFRACR_FRACLE; 1616 mmio_write_32(rcc_base + pll->pllxfracr, value); 1617 1618 stm32mp1_pll_config_output(pll_id, pllcfg); 1619 1620 return 0; 1621 } 1622 1623 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1624 { 1625 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1626 uint32_t pllxcsg = 0; 1627 1628 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1629 RCC_PLLNCSGR_MOD_PER_MASK; 1630 1631 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1632 RCC_PLLNCSGR_INC_STEP_MASK; 1633 1634 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1635 RCC_PLLNCSGR_SSCG_MODE_MASK; 1636 1637 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1638 1639 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1640 RCC_PLLNCR_SSCG_CTRL); 1641 } 1642 1643 static int stm32mp1_set_clksrc(unsigned int clksrc) 1644 { 1645 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1646 uint64_t timeout; 1647 1648 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1649 clksrc & RCC_SELR_SRC_MASK); 1650 1651 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1652 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1653 if (timeout_elapsed(timeout)) { 1654 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1655 clksrc_address, mmio_read_32(clksrc_address)); 1656 return -ETIMEDOUT; 1657 } 1658 } 1659 1660 return 0; 1661 } 1662 1663 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1664 { 1665 uint64_t timeout; 1666 1667 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1668 clkdiv & RCC_DIVR_DIV_MASK); 1669 1670 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1671 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1672 if (timeout_elapsed(timeout)) { 1673 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1674 clkdiv, address, mmio_read_32(address)); 1675 return -ETIMEDOUT; 1676 } 1677 } 1678 1679 return 0; 1680 } 1681 1682 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1683 { 1684 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1685 1686 /* 1687 * Binding clksrc : 1688 * bit15-4 offset 1689 * bit3: disable 1690 * bit2-0: MCOSEL[2:0] 1691 */ 1692 if ((clksrc & 0x8U) != 0U) { 1693 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1694 } else { 1695 mmio_clrsetbits_32(clksrc_address, 1696 RCC_MCOCFG_MCOSRC_MASK, 1697 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1698 mmio_clrsetbits_32(clksrc_address, 1699 RCC_MCOCFG_MCODIV_MASK, 1700 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1701 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1702 } 1703 } 1704 1705 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1706 { 1707 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1708 1709 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1710 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1711 mmio_clrsetbits_32(address, 1712 RCC_BDCR_RTCSRC_MASK, 1713 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 1714 1715 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1716 } 1717 1718 if (lse_css) { 1719 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1720 } 1721 } 1722 1723 static void stm32mp1_stgen_config(void) 1724 { 1725 uint32_t cntfid0; 1726 unsigned long rate; 1727 unsigned long long counter; 1728 1729 cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); 1730 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1731 1732 if (cntfid0 == rate) { 1733 return; 1734 } 1735 1736 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1737 counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1738 counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32; 1739 counter = (counter * rate / cntfid0); 1740 1741 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); 1742 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1743 mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); 1744 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1745 1746 write_cntfrq((u_register_t)rate); 1747 1748 /* Need to update timer with new frequency */ 1749 generic_delay_timer_init(); 1750 } 1751 1752 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1753 { 1754 unsigned long long cnt; 1755 1756 cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | 1757 mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1758 1759 cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U; 1760 1761 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1762 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); 1763 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1764 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1765 } 1766 1767 static void stm32mp1_pkcs_config(uint32_t pkcs) 1768 { 1769 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1770 uint32_t value = pkcs & 0xFU; 1771 uint32_t mask = 0xFU; 1772 1773 if ((pkcs & BIT(31)) != 0U) { 1774 mask <<= 4; 1775 value <<= 4; 1776 } 1777 1778 mmio_clrsetbits_32(address, mask, value); 1779 } 1780 1781 static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg, 1782 uint32_t *fracv, uint32_t *csg, 1783 bool *csg_set) 1784 { 1785 void *fdt; 1786 int ret; 1787 1788 if (fdt_get_address(&fdt) == 0) { 1789 return -FDT_ERR_NOTFOUND; 1790 } 1791 1792 ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB, 1793 pllcfg); 1794 if (ret < 0) { 1795 return -FDT_ERR_NOTFOUND; 1796 } 1797 1798 *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1799 1800 ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB, 1801 csg); 1802 1803 *csg_set = (ret == 0); 1804 1805 if (ret == -FDT_ERR_NOTFOUND) { 1806 ret = 0; 1807 } 1808 1809 return ret; 1810 } 1811 1812 int stm32mp1_clk_init(void) 1813 { 1814 uintptr_t rcc_base = stm32mp_rcc_base(); 1815 uint32_t pllfracv[_PLL_NB]; 1816 uint32_t pllcsg[_PLL_NB][PLLCSG_NB]; 1817 unsigned int clksrc[CLKSRC_NB]; 1818 unsigned int clkdiv[CLKDIV_NB]; 1819 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1820 int plloff[_PLL_NB]; 1821 int ret, len; 1822 enum stm32mp1_pll_id i; 1823 bool pllcsg_set[_PLL_NB]; 1824 bool pllcfg_valid[_PLL_NB]; 1825 bool lse_css = false; 1826 bool pll3_preserve = false; 1827 bool pll4_preserve = false; 1828 bool pll4_bootrom = false; 1829 const fdt32_t *pkcs_cell; 1830 void *fdt; 1831 int stgen_p = stm32mp1_clk_get_parent(STGEN_K); 1832 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); 1833 1834 if (fdt_get_address(&fdt) == 0) { 1835 return -FDT_ERR_NOTFOUND; 1836 } 1837 1838 /* Check status field to disable security */ 1839 if (!fdt_get_rcc_secure_status()) { 1840 mmio_write_32(rcc_base + RCC_TZCR, 0); 1841 } 1842 1843 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1844 clksrc); 1845 if (ret < 0) { 1846 return -FDT_ERR_NOTFOUND; 1847 } 1848 1849 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1850 clkdiv); 1851 if (ret < 0) { 1852 return -FDT_ERR_NOTFOUND; 1853 } 1854 1855 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1856 char name[12]; 1857 1858 snprintf(name, sizeof(name), "st,pll@%d", i); 1859 plloff[i] = fdt_rcc_subnode_offset(name); 1860 1861 pllcfg_valid[i] = fdt_check_node(plloff[i]); 1862 if (!pllcfg_valid[i]) { 1863 continue; 1864 } 1865 1866 ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i], 1867 &pllfracv[i], pllcsg[i], 1868 &pllcsg_set[i]); 1869 if (ret != 0) { 1870 return ret; 1871 } 1872 } 1873 1874 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1875 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1876 1877 /* 1878 * Switch ON oscillator found in device-tree. 1879 * Note: HSI already ON after BootROM stage. 1880 */ 1881 if (stm32mp1_osc[_LSI] != 0U) { 1882 stm32mp1_lsi_set(true); 1883 } 1884 if (stm32mp1_osc[_LSE] != 0U) { 1885 const char *name = stm32mp_osc_node_label[_LSE]; 1886 bool bypass, digbyp; 1887 uint32_t lsedrv; 1888 1889 bypass = fdt_clk_read_bool(name, "st,bypass"); 1890 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1891 lse_css = fdt_clk_read_bool(name, "st,css"); 1892 lsedrv = fdt_clk_read_uint32_default(name, "st,drive", 1893 LSEDRV_MEDIUM_HIGH); 1894 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1895 } 1896 if (stm32mp1_osc[_HSE] != 0U) { 1897 const char *name = stm32mp_osc_node_label[_HSE]; 1898 bool bypass, digbyp, css; 1899 1900 bypass = fdt_clk_read_bool(name, "st,bypass"); 1901 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 1902 css = fdt_clk_read_bool(name, "st,css"); 1903 stm32mp1_hse_enable(bypass, digbyp, css); 1904 } 1905 /* 1906 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1907 * => switch on CSI even if node is not present in device tree 1908 */ 1909 stm32mp1_csi_set(true); 1910 1911 /* Come back to HSI */ 1912 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1913 if (ret != 0) { 1914 return ret; 1915 } 1916 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1917 if (ret != 0) { 1918 return ret; 1919 } 1920 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1921 if (ret != 0) { 1922 return ret; 1923 } 1924 1925 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1926 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1927 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1928 clksrc[CLKSRC_PLL3], 1929 pllcfg[_PLL3], 1930 plloff[_PLL3]); 1931 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1932 clksrc[CLKSRC_PLL4], 1933 pllcfg[_PLL4], 1934 plloff[_PLL4]); 1935 } 1936 /* Don't initialize PLL4, when used by BOOTROM */ 1937 if ((stm32mp_get_boot_itf_selected() == 1938 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 1939 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { 1940 pll4_bootrom = true; 1941 pll4_preserve = true; 1942 } 1943 1944 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1945 if (((i == _PLL3) && pll3_preserve) || 1946 ((i == _PLL4) && pll4_preserve)) { 1947 continue; 1948 } 1949 1950 ret = stm32mp1_pll_stop(i); 1951 if (ret != 0) { 1952 return ret; 1953 } 1954 } 1955 1956 /* Configure HSIDIV */ 1957 if (stm32mp1_osc[_HSI] != 0U) { 1958 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1959 if (ret != 0) { 1960 return ret; 1961 } 1962 stm32mp1_stgen_config(); 1963 } 1964 1965 /* Select DIV */ 1966 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1967 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1968 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1969 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1970 if (ret != 0) { 1971 return ret; 1972 } 1973 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1974 if (ret != 0) { 1975 return ret; 1976 } 1977 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1978 if (ret != 0) { 1979 return ret; 1980 } 1981 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1982 if (ret != 0) { 1983 return ret; 1984 } 1985 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1986 if (ret != 0) { 1987 return ret; 1988 } 1989 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1990 if (ret != 0) { 1991 return ret; 1992 } 1993 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1994 if (ret != 0) { 1995 return ret; 1996 } 1997 1998 /* No ready bit for RTC */ 1999 mmio_write_32(rcc_base + RCC_RTCDIVR, 2000 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 2001 2002 /* Configure PLLs source */ 2003 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 2004 if (ret != 0) { 2005 return ret; 2006 } 2007 2008 if (!pll3_preserve) { 2009 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 2010 if (ret != 0) { 2011 return ret; 2012 } 2013 } 2014 2015 if (!pll4_preserve) { 2016 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 2017 if (ret != 0) { 2018 return ret; 2019 } 2020 } 2021 2022 /* Configure and start PLLs */ 2023 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2024 if (((i == _PLL3) && pll3_preserve) || 2025 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 2026 continue; 2027 } 2028 2029 if (!pllcfg_valid[i]) { 2030 continue; 2031 } 2032 2033 if ((i == _PLL4) && pll4_bootrom) { 2034 /* Set output divider if not done by the Bootrom */ 2035 stm32mp1_pll_config_output(i, pllcfg[i]); 2036 continue; 2037 } 2038 2039 ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]); 2040 if (ret != 0) { 2041 return ret; 2042 } 2043 2044 if (pllcsg_set[i]) { 2045 stm32mp1_pll_csg(i, pllcsg[i]); 2046 } 2047 2048 stm32mp1_pll_start(i); 2049 } 2050 /* Wait and start PLLs ouptut when ready */ 2051 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2052 if (!pllcfg_valid[i]) { 2053 continue; 2054 } 2055 2056 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 2057 if (ret != 0) { 2058 return ret; 2059 } 2060 } 2061 /* Wait LSE ready before to use it */ 2062 if (stm32mp1_osc[_LSE] != 0U) { 2063 stm32mp1_lse_wait(); 2064 } 2065 2066 /* Configure with expected clock source */ 2067 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 2068 if (ret != 0) { 2069 return ret; 2070 } 2071 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 2072 if (ret != 0) { 2073 return ret; 2074 } 2075 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 2076 if (ret != 0) { 2077 return ret; 2078 } 2079 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 2080 2081 /* Configure PKCK */ 2082 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 2083 if (pkcs_cell != NULL) { 2084 bool ckper_disabled = false; 2085 uint32_t j; 2086 uint32_t usbreg_bootrom = 0U; 2087 2088 if (pll4_bootrom) { 2089 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR); 2090 } 2091 2092 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 2093 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 2094 2095 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 2096 ckper_disabled = true; 2097 continue; 2098 } 2099 stm32mp1_pkcs_config(pkcs); 2100 } 2101 2102 /* 2103 * CKPER is source for some peripheral clocks 2104 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2105 * only if previous clock is still ON 2106 * => deactivated CKPER only after switching clock 2107 */ 2108 if (ckper_disabled) { 2109 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2110 } 2111 2112 if (pll4_bootrom) { 2113 uint32_t usbreg_value, usbreg_mask; 2114 const struct stm32mp1_clk_sel *sel; 2115 2116 sel = clk_sel_ref(_USBPHY_SEL); 2117 usbreg_mask = (uint32_t)sel->msk << sel->src; 2118 sel = clk_sel_ref(_USBO_SEL); 2119 usbreg_mask |= (uint32_t)sel->msk << sel->src; 2120 2121 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) & 2122 usbreg_mask; 2123 usbreg_bootrom &= usbreg_mask; 2124 if (usbreg_bootrom != usbreg_value) { 2125 VERBOSE("forbidden new USB clk path\n"); 2126 VERBOSE("vs bootrom on USB boot\n"); 2127 return -FDT_ERR_BADVALUE; 2128 } 2129 } 2130 } 2131 2132 /* Switch OFF HSI if not found in device-tree */ 2133 if (stm32mp1_osc[_HSI] == 0U) { 2134 stm32mp1_hsi_set(false); 2135 } 2136 stm32mp1_stgen_config(); 2137 2138 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2139 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2140 RCC_DDRITFCR_DDRCKMOD_MASK, 2141 RCC_DDRITFCR_DDRCKMOD_SSR << 2142 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2143 2144 return 0; 2145 } 2146 2147 static void stm32mp1_osc_clk_init(const char *name, 2148 enum stm32mp_osc_id index) 2149 { 2150 uint32_t frequency; 2151 2152 if (fdt_osc_read_freq(name, &frequency) == 0) { 2153 stm32mp1_osc[index] = frequency; 2154 } 2155 } 2156 2157 static void stm32mp1_osc_init(void) 2158 { 2159 enum stm32mp_osc_id i; 2160 2161 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2162 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2163 } 2164 } 2165 2166 #ifdef STM32MP_SHARED_RESOURCES 2167 /* 2168 * Get the parent ID of the target parent clock, for tagging as secure 2169 * shared clock dependencies. 2170 */ 2171 static int get_parent_id_parent(unsigned int parent_id) 2172 { 2173 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2174 enum stm32mp1_pll_id pll_id; 2175 uint32_t p_sel; 2176 uintptr_t rcc_base = stm32mp_rcc_base(); 2177 2178 switch (parent_id) { 2179 case _ACLK: 2180 case _PCLK4: 2181 case _PCLK5: 2182 s = _AXIS_SEL; 2183 break; 2184 case _PLL1_P: 2185 case _PLL1_Q: 2186 case _PLL1_R: 2187 pll_id = _PLL1; 2188 break; 2189 case _PLL2_P: 2190 case _PLL2_Q: 2191 case _PLL2_R: 2192 pll_id = _PLL2; 2193 break; 2194 case _PLL3_P: 2195 case _PLL3_Q: 2196 case _PLL3_R: 2197 pll_id = _PLL3; 2198 break; 2199 case _PLL4_P: 2200 case _PLL4_Q: 2201 case _PLL4_R: 2202 pll_id = _PLL4; 2203 break; 2204 case _PCLK1: 2205 case _PCLK2: 2206 case _HCLK2: 2207 case _HCLK6: 2208 case _CK_PER: 2209 case _CK_MPU: 2210 case _CK_MCU: 2211 case _USB_PHY_48: 2212 /* We do not expect to access these */ 2213 panic(); 2214 break; 2215 default: 2216 /* Other parents have no parent */ 2217 return -1; 2218 } 2219 2220 if (s != _UNKNOWN_SEL) { 2221 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2222 2223 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2224 sel->msk; 2225 2226 if (p_sel < sel->nb_parent) { 2227 return (int)sel->parent[p_sel]; 2228 } 2229 } else { 2230 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2231 2232 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2233 RCC_SELR_REFCLK_SRC_MASK; 2234 2235 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2236 return (int)pll->refclk[p_sel]; 2237 } 2238 } 2239 2240 VERBOSE("No parent selected for %s\n", 2241 stm32mp1_clk_parent_name[parent_id]); 2242 2243 return -1; 2244 } 2245 2246 static void secure_parent_clocks(unsigned long parent_id) 2247 { 2248 int grandparent_id; 2249 2250 switch (parent_id) { 2251 case _PLL3_P: 2252 case _PLL3_Q: 2253 case _PLL3_R: 2254 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2255 break; 2256 2257 /* These clocks are always secure when RCC is secure */ 2258 case _ACLK: 2259 case _HCLK2: 2260 case _HCLK6: 2261 case _PCLK4: 2262 case _PCLK5: 2263 case _PLL1_P: 2264 case _PLL1_Q: 2265 case _PLL1_R: 2266 case _PLL2_P: 2267 case _PLL2_Q: 2268 case _PLL2_R: 2269 case _HSI: 2270 case _HSI_KER: 2271 case _LSI: 2272 case _CSI: 2273 case _CSI_KER: 2274 case _HSE: 2275 case _HSE_KER: 2276 case _HSE_KER_DIV2: 2277 case _HSE_RTC: 2278 case _LSE: 2279 break; 2280 2281 default: 2282 VERBOSE("Cannot secure parent clock %s\n", 2283 stm32mp1_clk_parent_name[parent_id]); 2284 panic(); 2285 } 2286 2287 grandparent_id = get_parent_id_parent(parent_id); 2288 if (grandparent_id >= 0) { 2289 secure_parent_clocks(grandparent_id); 2290 } 2291 } 2292 2293 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2294 { 2295 int parent_id; 2296 2297 if (!stm32mp1_rcc_is_secure()) { 2298 return; 2299 } 2300 2301 switch (clock_id) { 2302 case PLL1: 2303 case PLL2: 2304 /* PLL1/PLL2 are always secure: nothing to do */ 2305 break; 2306 case PLL3: 2307 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2308 break; 2309 case PLL4: 2310 ERROR("PLL4 cannot be secured\n"); 2311 panic(); 2312 break; 2313 default: 2314 /* Others are expected gateable clock */ 2315 parent_id = stm32mp1_clk_get_parent(clock_id); 2316 if (parent_id < 0) { 2317 INFO("No parent found for clock %lu\n", clock_id); 2318 } else { 2319 secure_parent_clocks(parent_id); 2320 } 2321 break; 2322 } 2323 } 2324 #endif /* STM32MP_SHARED_RESOURCES */ 2325 2326 static void sync_earlyboot_clocks_state(void) 2327 { 2328 unsigned int idx; 2329 const unsigned long secure_enable[] = { 2330 AXIDCG, 2331 BSEC, 2332 DDRC1, DDRC1LP, 2333 DDRC2, DDRC2LP, 2334 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2335 DDRPHYC, DDRPHYCLP, 2336 RTCAPB, 2337 TZC1, TZC2, 2338 TZPC, 2339 STGEN_K, 2340 }; 2341 2342 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2343 stm32mp_clk_enable(secure_enable[idx]); 2344 } 2345 } 2346 2347 static const struct clk_ops stm32mp_clk_ops = { 2348 .enable = stm32mp_clk_enable, 2349 .disable = stm32mp_clk_disable, 2350 .is_enabled = stm32mp_clk_is_enabled, 2351 .get_rate = stm32mp_clk_get_rate, 2352 .get_parent = stm32mp1_clk_get_parent, 2353 }; 2354 2355 int stm32mp1_clk_probe(void) 2356 { 2357 stm32mp1_osc_init(); 2358 2359 sync_earlyboot_clocks_state(); 2360 2361 clk_register(&stm32mp_clk_ops); 2362 2363 return 0; 2364 } 2365