1 /* 2 * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <lib/el3_runtime/context_mgmt.h> 13 #include <lib/extensions/sme.h> 14 #include <lib/extensions/sve.h> 15 16 static bool feat_sme_supported(void) 17 { 18 uint64_t features; 19 20 features = read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SME_SHIFT; 21 return (features & ID_AA64PFR1_EL1_SME_MASK) != 0U; 22 } 23 24 static bool feat_sme_fa64_supported(void) 25 { 26 uint64_t features; 27 28 features = read_id_aa64smfr0_el1(); 29 return (features & ID_AA64SMFR0_EL1_FA64_BIT) != 0U; 30 } 31 32 void sme_enable(cpu_context_t *context) 33 { 34 u_register_t reg; 35 u_register_t cptr_el3; 36 el3_state_t *state; 37 38 /* Make sure SME is implemented in hardware before continuing. */ 39 if (!feat_sme_supported()) { 40 return; 41 } 42 43 /* Get the context state. */ 44 state = get_el3state_ctx(context); 45 46 /* Enable SME in CPTR_EL3. */ 47 reg = read_ctx_reg(state, CTX_CPTR_EL3); 48 reg |= ESM_BIT; 49 write_ctx_reg(state, CTX_CPTR_EL3, reg); 50 51 /* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */ 52 reg = read_ctx_reg(state, CTX_SCR_EL3); 53 reg |= SCR_ENTP2_BIT; 54 write_ctx_reg(state, CTX_SCR_EL3, reg); 55 56 /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */ 57 cptr_el3 = read_cptr_el3(); 58 write_cptr_el3(cptr_el3 | ESM_BIT); 59 60 /* 61 * Set the max LEN value and FA64 bit. This register is set up globally 62 * to be the least restrictive, then lower ELs can restrict as needed 63 * using SMCR_EL2 and SMCR_EL1. 64 */ 65 reg = SMCR_ELX_LEN_MASK; 66 if (feat_sme_fa64_supported()) { 67 VERBOSE("[SME] FA64 enabled\n"); 68 reg |= SMCR_ELX_FA64_BIT; 69 } 70 write_smcr_el3(reg); 71 72 /* Reset CPTR_EL3 value. */ 73 write_cptr_el3(cptr_el3); 74 75 /* Enable SVE/FPU in addition to SME. */ 76 sve_enable(context); 77 } 78 79 void sme_disable(cpu_context_t *context) 80 { 81 u_register_t reg; 82 el3_state_t *state; 83 84 /* Make sure SME is implemented in hardware before continuing. */ 85 if (!feat_sme_supported()) { 86 return; 87 } 88 89 /* Get the context state. */ 90 state = get_el3state_ctx(context); 91 92 /* Disable SME, SVE, and FPU since they all share registers. */ 93 reg = read_ctx_reg(state, CTX_CPTR_EL3); 94 reg &= ~ESM_BIT; /* Trap SME */ 95 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 96 reg |= TFP_BIT; /* Trap FPU/SIMD */ 97 write_ctx_reg(state, CTX_CPTR_EL3, reg); 98 99 /* Disable access to TPIDR2_EL0. */ 100 reg = read_ctx_reg(state, CTX_SCR_EL3); 101 reg &= ~SCR_ENTP2_BIT; 102 write_ctx_reg(state, CTX_SCR_EL3, reg); 103 } 104