1 2 /* 3 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <platform_def.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <lib/xlat_tables/xlat_tables_v2.h> 13 #include <services/el3_spmc_ffa_memory.h> 14 15 #include <plat/common/platform.h> 16 #include "qemu_private.h" 17 18 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 19 DEVICE0_SIZE, \ 20 MT_DEVICE | MT_RW | MT_SECURE) 21 22 #ifdef DEVICE1_BASE 23 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 24 DEVICE1_SIZE, \ 25 MT_DEVICE | MT_RW | MT_SECURE) 26 #endif 27 28 #ifdef DEVICE2_BASE 29 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 30 DEVICE2_SIZE, \ 31 MT_DEVICE | MT_RW | MT_SECURE) 32 #endif 33 34 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ 35 SHARED_RAM_SIZE, \ 36 MT_DEVICE | MT_RW | MT_SECURE) 37 38 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ 39 MT_MEMORY | MT_RW | MT_SECURE) 40 41 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ 42 MT_MEMORY | MT_RW | MT_NS) 43 44 #define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \ 45 MT_MEMORY | MT_RO | MT_SECURE) 46 47 #define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \ 48 MT_MEMORY | MT_RO | MT_SECURE) 49 50 /* 51 * Table of regions for various BL stages to map using the MMU. 52 * This doesn't include TZRAM as the 'mem_layout' argument passed to 53 * arm_configure_mmu_elx() will give the available subset of that, 54 */ 55 #ifdef IMAGE_BL1 56 static const mmap_region_t plat_qemu_mmap[] = { 57 MAP_FLASH0, 58 MAP_FLASH1, 59 MAP_SHARED_RAM, 60 MAP_DEVICE0, 61 #ifdef MAP_DEVICE1 62 MAP_DEVICE1, 63 #endif 64 #ifdef MAP_DEVICE2 65 MAP_DEVICE2, 66 #endif 67 {0} 68 }; 69 #endif 70 #ifdef IMAGE_BL2 71 static const mmap_region_t plat_qemu_mmap[] = { 72 MAP_FLASH0, 73 MAP_FLASH1, 74 MAP_SHARED_RAM, 75 MAP_DEVICE0, 76 #ifdef MAP_DEVICE1 77 MAP_DEVICE1, 78 #endif 79 #ifdef MAP_DEVICE2 80 MAP_DEVICE2, 81 #endif 82 MAP_NS_DRAM0, 83 #if SPM_MM 84 QEMU_SP_IMAGE_MMAP, 85 #else 86 MAP_BL32_MEM, 87 #endif 88 {0} 89 }; 90 #endif 91 #ifdef IMAGE_BL31 92 static const mmap_region_t plat_qemu_mmap[] = { 93 MAP_SHARED_RAM, 94 MAP_DEVICE0, 95 #ifdef MAP_DEVICE1 96 MAP_DEVICE1, 97 #endif 98 #ifdef MAP_DEVICE2 99 MAP_DEVICE2, 100 #endif 101 #if SPM_MM 102 MAP_NS_DRAM0, 103 QEMU_SPM_BUF_EL3_MMAP, 104 #elif !SPMC_AT_EL3 105 MAP_BL32_MEM, 106 #endif 107 {0} 108 }; 109 #endif 110 #ifdef IMAGE_BL32 111 static const mmap_region_t plat_qemu_mmap[] = { 112 MAP_SHARED_RAM, 113 MAP_DEVICE0, 114 #ifdef MAP_DEVICE1 115 MAP_DEVICE1, 116 #endif 117 #ifdef MAP_DEVICE2 118 MAP_DEVICE2, 119 #endif 120 {0} 121 }; 122 #endif 123 124 /******************************************************************************* 125 * Macro generating the code for the function setting up the pagetables as per 126 * the platform memory map & initialize the mmu, for the given exception level 127 ******************************************************************************/ 128 129 #define DEFINE_CONFIGURE_MMU_EL(_el) \ 130 void qemu_configure_mmu_##_el(unsigned long total_base, \ 131 unsigned long total_size, \ 132 unsigned long code_start, \ 133 unsigned long code_limit, \ 134 unsigned long ro_start, \ 135 unsigned long ro_limit, \ 136 unsigned long coh_start, \ 137 unsigned long coh_limit) \ 138 { \ 139 mmap_add_region(total_base, total_base, \ 140 total_size, \ 141 MT_MEMORY | MT_RW | MT_SECURE); \ 142 mmap_add_region(code_start, code_start, \ 143 code_limit - code_start, \ 144 MT_CODE | MT_SECURE); \ 145 mmap_add_region(ro_start, ro_start, \ 146 ro_limit - ro_start, \ 147 MT_RO_DATA | MT_SECURE); \ 148 mmap_add_region(coh_start, coh_start, \ 149 coh_limit - coh_start, \ 150 MT_DEVICE | MT_RW | MT_SECURE); \ 151 mmap_add(plat_qemu_mmap); \ 152 init_xlat_tables(); \ 153 \ 154 enable_mmu_##_el(0); \ 155 } 156 157 /* Define EL1 and EL3 variants of the function initialising the MMU */ 158 #ifdef __aarch64__ 159 DEFINE_CONFIGURE_MMU_EL(el1) 160 DEFINE_CONFIGURE_MMU_EL(el3) 161 #else 162 DEFINE_CONFIGURE_MMU_EL(svc_mon) 163 #endif 164 165 #if MEASURED_BOOT || TRUSTED_BOARD_BOOT 166 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 167 { 168 return get_mbedtls_heap_helper(heap_addr, heap_size); 169 } 170 #endif 171 172 #if SPMC_AT_EL3 173 /* 174 * When using the EL3 SPMC implementation allocate the datastore 175 * for tracking shared memory descriptors in normal memory. 176 */ 177 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 64 * 1024 178 179 uint8_t plat_spmc_shmem_datastore[PLAT_SPMC_SHMEM_DATASTORE_SIZE]; 180 181 int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) 182 { 183 *datastore = plat_spmc_shmem_datastore; 184 *size = PLAT_SPMC_SHMEM_DATASTORE_SIZE; 185 return 0; 186 } 187 188 int plat_spmc_shmem_begin(struct ffa_mtd *desc) 189 { 190 return 0; 191 } 192 193 int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) 194 { 195 return 0; 196 } 197 #endif 198