1 /* 2 * Copyright (c) 2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_X2_H 8 #define CORTEX_X2_H 9 10 #define CORTEX_X2_MIDR U(0x410FD480) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 16 17 /******************************************************************************* 18 * CPU Extended Control register 2 specific definitions 19 ******************************************************************************/ 20 #define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5 21 22 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11) 23 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 24 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) 25 26 /******************************************************************************* 27 * CPU Power Control register specific definitions 28 ******************************************************************************/ 29 #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 30 #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 31 32 /******************************************************************************* 33 * CPU Auxiliary Control Register 5 definitions 34 ******************************************************************************/ 35 #define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 36 37 #endif /* CORTEX_X2_H */ 38