1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/clk.h> 10 #include <drivers/st/stm32_gpio.h> 11 #include <drivers/st/stm32_iwdg.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <libfdt.h> 15 16 #include <platform_def.h> 17 18 /* Internal layout of the 32bit OTP word board_id */ 19 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 20 #define BOARD_ID_BOARD_NB_SHIFT 16 21 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 22 #define BOARD_ID_VARCPN_SHIFT 12 23 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 24 #define BOARD_ID_REVISION_SHIFT 8 25 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 26 #define BOARD_ID_VARFG_SHIFT 4 27 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 28 29 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 30 BOARD_ID_BOARD_NB_SHIFT) 31 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 32 BOARD_ID_VARCPN_SHIFT) 33 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 34 BOARD_ID_REVISION_SHIFT) 35 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 36 BOARD_ID_VARFG_SHIFT) 37 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 38 39 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) 40 #define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00) 41 #define TAMP_BOOT_MODE_ITF_SHIFT 8 42 43 #if defined(IMAGE_BL2) 44 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 45 STM32MP_SYSRAM_SIZE, \ 46 MT_MEMORY | \ 47 MT_RW | \ 48 MT_SECURE | \ 49 MT_EXECUTE_NEVER) 50 #elif defined(IMAGE_BL32) 51 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 52 STM32MP_SEC_SYSRAM_SIZE, \ 53 MT_MEMORY | \ 54 MT_RW | \ 55 MT_SECURE | \ 56 MT_EXECUTE_NEVER) 57 58 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 59 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 60 STM32MP_NS_SYSRAM_SIZE, \ 61 MT_DEVICE | \ 62 MT_RW | \ 63 MT_NS | \ 64 MT_EXECUTE_NEVER) 65 #endif 66 67 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 68 STM32MP1_DEVICE1_SIZE, \ 69 MT_DEVICE | \ 70 MT_RW | \ 71 MT_SECURE | \ 72 MT_EXECUTE_NEVER) 73 74 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 75 STM32MP1_DEVICE2_SIZE, \ 76 MT_DEVICE | \ 77 MT_RW | \ 78 MT_SECURE | \ 79 MT_EXECUTE_NEVER) 80 81 #if defined(IMAGE_BL2) 82 static const mmap_region_t stm32mp1_mmap[] = { 83 MAP_SEC_SYSRAM, 84 MAP_DEVICE1, 85 #if STM32MP_RAW_NAND 86 MAP_DEVICE2, 87 #endif 88 {0} 89 }; 90 #endif 91 #if defined(IMAGE_BL32) 92 static const mmap_region_t stm32mp1_mmap[] = { 93 MAP_SEC_SYSRAM, 94 MAP_NS_SYSRAM, 95 MAP_DEVICE1, 96 MAP_DEVICE2, 97 {0} 98 }; 99 #endif 100 101 void configure_mmu(void) 102 { 103 mmap_add(stm32mp1_mmap); 104 init_xlat_tables(); 105 106 enable_mmu_svc_mon(0); 107 } 108 109 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 110 { 111 if (bank == GPIO_BANK_Z) { 112 return GPIOZ_BASE; 113 } 114 115 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 116 117 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 118 } 119 120 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 121 { 122 if (bank == GPIO_BANK_Z) { 123 return 0; 124 } 125 126 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 127 128 return bank * GPIO_BANK_OFFSET; 129 } 130 131 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 132 { 133 if (bank == GPIO_BANK_Z) { 134 return true; 135 } 136 137 return false; 138 } 139 140 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 141 { 142 if (bank == GPIO_BANK_Z) { 143 return GPIOZ; 144 } 145 146 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 147 148 return GPIOA + (bank - GPIO_BANK_A); 149 } 150 151 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 152 { 153 switch (bank) { 154 case GPIO_BANK_A: 155 case GPIO_BANK_B: 156 case GPIO_BANK_C: 157 case GPIO_BANK_D: 158 case GPIO_BANK_E: 159 case GPIO_BANK_F: 160 case GPIO_BANK_G: 161 case GPIO_BANK_H: 162 case GPIO_BANK_I: 163 case GPIO_BANK_J: 164 case GPIO_BANK_K: 165 return fdt_path_offset(fdt, "/soc/pin-controller"); 166 case GPIO_BANK_Z: 167 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 168 default: 169 panic(); 170 } 171 } 172 173 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 174 /* 175 * UART Management 176 */ 177 static const uintptr_t stm32mp1_uart_addresses[8] = { 178 USART1_BASE, 179 USART2_BASE, 180 USART3_BASE, 181 UART4_BASE, 182 UART5_BASE, 183 USART6_BASE, 184 UART7_BASE, 185 UART8_BASE, 186 }; 187 188 uintptr_t get_uart_address(uint32_t instance_nb) 189 { 190 if ((instance_nb == 0U) || 191 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 192 return 0U; 193 } 194 195 return stm32mp1_uart_addresses[instance_nb - 1U]; 196 } 197 #endif 198 199 #if STM32MP_USB_PROGRAMMER 200 struct gpio_bank_pin_list { 201 uint32_t bank; 202 uint32_t pin; 203 }; 204 205 static const struct gpio_bank_pin_list gpio_list[] = { 206 { /* USART2_RX: GPIOA3 */ 207 .bank = 0U, 208 .pin = 3U, 209 }, 210 { /* USART3_RX: GPIOB12 */ 211 .bank = 1U, 212 .pin = 12U, 213 }, 214 { /* UART4_RX: GPIOB2 */ 215 .bank = 1U, 216 .pin = 2U, 217 }, 218 { /* UART5_RX: GPIOB4 */ 219 .bank = 1U, 220 .pin = 5U, 221 }, 222 { /* USART6_RX: GPIOC7 */ 223 .bank = 2U, 224 .pin = 7U, 225 }, 226 { /* UART7_RX: GPIOF6 */ 227 .bank = 5U, 228 .pin = 6U, 229 }, 230 { /* UART8_RX: GPIOE0 */ 231 .bank = 4U, 232 .pin = 0U, 233 }, 234 }; 235 236 void stm32mp1_deconfigure_uart_pins(void) 237 { 238 size_t i; 239 240 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) { 241 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin); 242 } 243 } 244 #endif 245 246 uint32_t stm32mp_get_chip_version(void) 247 { 248 uint32_t version = 0U; 249 250 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 251 INFO("Cannot get CPU version, debug disabled\n"); 252 return 0U; 253 } 254 255 return version; 256 } 257 258 uint32_t stm32mp_get_chip_dev_id(void) 259 { 260 uint32_t dev_id; 261 262 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 263 INFO("Use default chip ID, debug disabled\n"); 264 dev_id = STM32MP1_CHIP_ID; 265 } 266 267 return dev_id; 268 } 269 270 static uint32_t get_part_number(void) 271 { 272 static uint32_t part_number; 273 274 if (part_number != 0U) { 275 return part_number; 276 } 277 278 if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) { 279 panic(); 280 } 281 282 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 283 PART_NUMBER_OTP_PART_SHIFT; 284 285 part_number |= stm32mp_get_chip_dev_id() << 16; 286 287 return part_number; 288 } 289 290 static uint32_t get_cpu_package(void) 291 { 292 uint32_t package; 293 294 if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { 295 panic(); 296 } 297 298 package = (package & PACKAGE_OTP_PKG_MASK) >> 299 PACKAGE_OTP_PKG_SHIFT; 300 301 return package; 302 } 303 304 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 305 { 306 char *cpu_s, *cpu_r, *pkg; 307 308 /* MPUs Part Numbers */ 309 switch (get_part_number()) { 310 case STM32MP157C_PART_NB: 311 cpu_s = "157C"; 312 break; 313 case STM32MP157A_PART_NB: 314 cpu_s = "157A"; 315 break; 316 case STM32MP153C_PART_NB: 317 cpu_s = "153C"; 318 break; 319 case STM32MP153A_PART_NB: 320 cpu_s = "153A"; 321 break; 322 case STM32MP151C_PART_NB: 323 cpu_s = "151C"; 324 break; 325 case STM32MP151A_PART_NB: 326 cpu_s = "151A"; 327 break; 328 case STM32MP157F_PART_NB: 329 cpu_s = "157F"; 330 break; 331 case STM32MP157D_PART_NB: 332 cpu_s = "157D"; 333 break; 334 case STM32MP153F_PART_NB: 335 cpu_s = "153F"; 336 break; 337 case STM32MP153D_PART_NB: 338 cpu_s = "153D"; 339 break; 340 case STM32MP151F_PART_NB: 341 cpu_s = "151F"; 342 break; 343 case STM32MP151D_PART_NB: 344 cpu_s = "151D"; 345 break; 346 default: 347 cpu_s = "????"; 348 break; 349 } 350 351 /* Package */ 352 switch (get_cpu_package()) { 353 case PKG_AA_LFBGA448: 354 pkg = "AA"; 355 break; 356 case PKG_AB_LFBGA354: 357 pkg = "AB"; 358 break; 359 case PKG_AC_TFBGA361: 360 pkg = "AC"; 361 break; 362 case PKG_AD_TFBGA257: 363 pkg = "AD"; 364 break; 365 default: 366 pkg = "??"; 367 break; 368 } 369 370 /* REVISION */ 371 switch (stm32mp_get_chip_version()) { 372 case STM32MP1_REV_B: 373 cpu_r = "B"; 374 break; 375 case STM32MP1_REV_Z: 376 cpu_r = "Z"; 377 break; 378 default: 379 cpu_r = "?"; 380 break; 381 } 382 383 snprintf(name, STM32_SOC_NAME_SIZE, 384 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 385 } 386 387 void stm32mp_print_cpuinfo(void) 388 { 389 char name[STM32_SOC_NAME_SIZE]; 390 391 stm32mp_get_soc_name(name); 392 NOTICE("CPU: %s\n", name); 393 } 394 395 void stm32mp_print_boardinfo(void) 396 { 397 uint32_t board_id; 398 uint32_t board_otp; 399 int bsec_node, bsec_board_id_node; 400 void *fdt; 401 const fdt32_t *cuint; 402 403 if (fdt_get_address(&fdt) == 0) { 404 panic(); 405 } 406 407 bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT); 408 if (bsec_node < 0) { 409 return; 410 } 411 412 bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id"); 413 if (bsec_board_id_node <= 0) { 414 return; 415 } 416 417 cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL); 418 if (cuint == NULL) { 419 panic(); 420 } 421 422 board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t); 423 424 if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) { 425 ERROR("BSEC: PART_NUMBER_OTP Error\n"); 426 return; 427 } 428 429 if (board_id != 0U) { 430 char rev[2]; 431 432 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 433 rev[1] = '\0'; 434 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 435 BOARD_ID2NB(board_id), 436 BOARD_ID2VARCPN(board_id), 437 BOARD_ID2VARFG(board_id), 438 rev, 439 BOARD_ID2BOM(board_id)); 440 } 441 } 442 443 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 444 bool stm32mp_is_single_core(void) 445 { 446 switch (get_part_number()) { 447 case STM32MP151A_PART_NB: 448 case STM32MP151C_PART_NB: 449 case STM32MP151D_PART_NB: 450 case STM32MP151F_PART_NB: 451 return true; 452 default: 453 return false; 454 } 455 } 456 457 /* Return true when device is in closed state */ 458 bool stm32mp_is_closed_device(void) 459 { 460 uint32_t value; 461 462 if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) || 463 (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) { 464 return true; 465 } 466 467 return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED; 468 } 469 470 uint32_t stm32_iwdg_get_instance(uintptr_t base) 471 { 472 switch (base) { 473 case IWDG1_BASE: 474 return IWDG1_INST; 475 case IWDG2_BASE: 476 return IWDG2_INST; 477 default: 478 panic(); 479 } 480 } 481 482 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 483 { 484 uint32_t iwdg_cfg = 0U; 485 uint32_t otp_value; 486 487 #if defined(IMAGE_BL2) 488 if (bsec_shadow_register(HW2_OTP) != BSEC_OK) { 489 panic(); 490 } 491 #endif 492 493 if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) { 494 panic(); 495 } 496 497 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 498 iwdg_cfg |= IWDG_HW_ENABLED; 499 } 500 501 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 502 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 503 } 504 505 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 506 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 507 } 508 509 return iwdg_cfg; 510 } 511 512 #if defined(IMAGE_BL2) 513 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 514 { 515 uint32_t otp; 516 uint32_t result; 517 518 if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) { 519 panic(); 520 } 521 522 if ((flags & IWDG_DISABLE_ON_STOP) != 0U) { 523 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 524 } 525 526 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) { 527 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 528 } 529 530 result = bsec_write_otp(otp, HW2_OTP); 531 if (result != BSEC_OK) { 532 return result; 533 } 534 535 /* Sticky lock OTP_IWDG (read and write) */ 536 if (!bsec_write_sr_lock(HW2_OTP, 1U) || 537 !bsec_write_sw_lock(HW2_OTP, 1U)) { 538 return BSEC_LOCK_FAIL; 539 } 540 541 return BSEC_OK; 542 } 543 #endif 544 545 #if STM32MP_USE_STM32IMAGE 546 /* Get the non-secure DDR size */ 547 uint32_t stm32mp_get_ddr_ns_size(void) 548 { 549 static uint32_t ddr_ns_size; 550 uint32_t ddr_size; 551 552 if (ddr_ns_size != 0U) { 553 return ddr_ns_size; 554 } 555 556 ddr_size = dt_get_ddr_size(); 557 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 558 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 559 panic(); 560 } 561 562 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 563 564 return ddr_ns_size; 565 } 566 #endif /* STM32MP_USE_STM32IMAGE */ 567 568 void stm32_save_boot_interface(uint32_t interface, uint32_t instance) 569 { 570 uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 571 572 clk_enable(RTCAPB); 573 574 mmio_clrsetbits_32(bkpr_itf_idx, 575 TAMP_BOOT_MODE_ITF_MASK, 576 ((interface << 4) | (instance & 0xFU)) << 577 TAMP_BOOT_MODE_ITF_SHIFT); 578 579 clk_disable(RTCAPB); 580 } 581 582 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) 583 { 584 static uint32_t itf; 585 586 if (itf == 0U) { 587 uint32_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 588 589 clk_enable(RTCAPB); 590 591 itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >> 592 TAMP_BOOT_MODE_ITF_SHIFT; 593 594 clk_disable(RTCAPB); 595 } 596 597 *interface = itf >> 4; 598 *instance = itf & 0xFU; 599 } 600