1 /* 2 * Copyright (c) 2019, ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GIC600_MULTICHIP_PRIVATE_H 8 #define GIC600_MULTICHIP_PRIVATE_H 9 10 #include <drivers/arm/gic600_multichip.h> 11 12 #include "gicv3_private.h" 13 14 /* GIC600 GICD multichip related offsets */ 15 #define GICD_CHIPSR U(0xC000) 16 #define GICD_DCHIPR U(0xC004) 17 #define GICD_CHIPR U(0xC008) 18 19 /* GIC600 GICD multichip related masks */ 20 #define GICD_CHIPRx_PUP_BIT BIT_64(1) 21 #define GICD_CHIPRx_SOCKET_STATE BIT_64(0) 22 #define GICD_DCHIPR_PUP_BIT BIT_32(0) 23 #define GICD_CHIPSR_RTS_MASK (BIT_32(4) | BIT_32(5)) 24 25 /* GIC600 GICD multichip related shifts */ 26 #define GICD_CHIPRx_ADDR_SHIFT 16 27 #define GICD_CHIPSR_RTS_SHIFT 4 28 #define GICD_DCHIPR_RT_OWNER_SHIFT 4 29 30 /* Other shifts and masks remain the same between GIC-600 and GIC-700. */ 31 #define GIC_700_SPI_BLOCK_MIN_SHIFT 9 32 #define GIC_700_SPI_BLOCKS_SHIFT 3 33 #define GIC_600_SPI_BLOCK_MIN_SHIFT 10 34 #define GIC_600_SPI_BLOCKS_SHIFT 5 35 36 #define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0) 37 #define GICD_CHIPSR_RTS_STATE_UPDATING U(1) 38 #define GICD_CHIPSR_RTS_STATE_CONSISTENT U(2) 39 40 /* SPI interrupt id minimum and maximum range */ 41 #define GIC600_SPI_ID_MIN 32 42 #define GIC600_SPI_ID_MAX 960 43 44 /* Number of retries for PUP update */ 45 #define GICD_PUP_UPDATE_RETRIES 10000 46 47 #define SPI_MIN_INDEX 0 48 #define SPI_MAX_INDEX 1 49 50 #define SPI_BLOCK_MIN_VALUE(spi_id_min) \ 51 (((spi_id_min) - GIC600_SPI_ID_MIN) / \ 52 GIC600_SPI_ID_MIN) 53 #define SPI_BLOCKS_VALUE(spi_id_min, spi_id_max) \ 54 (((spi_id_max) - (spi_id_min) + 1) / \ 55 GIC600_SPI_ID_MIN) 56 #define GICD_CHIPR_VALUE_GIC_700(chip_addr, spi_block_min, spi_blocks) \ 57 (((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \ 58 ((spi_block_min) << GIC_700_SPI_BLOCK_MIN_SHIFT) | \ 59 ((spi_blocks) << GIC_700_SPI_BLOCKS_SHIFT)) 60 #define GICD_CHIPR_VALUE_GIC_600(chip_addr, spi_block_min, spi_blocks) \ 61 (((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \ 62 ((spi_block_min) << GIC_600_SPI_BLOCK_MIN_SHIFT) | \ 63 ((spi_blocks) << GIC_600_SPI_BLOCKS_SHIFT)) 64 65 /* 66 * Multichip data assertion macros 67 */ 68 /* Set bits from 0 to ((spi_id_max + 1) / 32) */ 69 #define SPI_BLOCKS_TILL_MAX(spi_id_max) ((1 << (((spi_id_max) + 1) >> 5)) - 1) 70 /* Set bits from 0 to (spi_id_min / 32) */ 71 #define SPI_BLOCKS_TILL_MIN(spi_id_min) ((1 << ((spi_id_min) >> 5)) - 1) 72 /* Set bits from (spi_id_min / 32) to ((spi_id_max + 1) / 32) */ 73 #define BLOCKS_OF_32(spi_id_min, spi_id_max) \ 74 SPI_BLOCKS_TILL_MAX(spi_id_max) ^ \ 75 SPI_BLOCKS_TILL_MIN(spi_id_min) 76 77 /******************************************************************************* 78 * GIC-600 multichip operation related helper functions 79 ******************************************************************************/ 80 static inline uint32_t read_gicd_dchipr(uintptr_t base) 81 { 82 return mmio_read_32(base + GICD_DCHIPR); 83 } 84 85 static inline uint64_t read_gicd_chipr_n(uintptr_t base, uint8_t n) 86 { 87 return mmio_read_64(base + (GICD_CHIPR + (8U * n))); 88 } 89 90 static inline uint32_t read_gicd_chipsr(uintptr_t base) 91 { 92 return mmio_read_32(base + GICD_CHIPSR); 93 } 94 95 static inline void write_gicd_dchipr(uintptr_t base, uint32_t val) 96 { 97 mmio_write_32(base + GICD_DCHIPR, val); 98 } 99 100 static inline void write_gicd_chipr_n(uintptr_t base, uint8_t n, uint64_t val) 101 { 102 mmio_write_64(base + (GICD_CHIPR + (8U * n)), val); 103 } 104 105 #endif /* GIC600_MULTICHIP_PRIVATE_H */ 106