1 /* 2 * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <limits.h> 10 #include <stdint.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <common/debug.h> 17 #include <drivers/clk.h> 18 #include <drivers/delay_timer.h> 19 #include <drivers/raw_nand.h> 20 #include <drivers/st/stm32_fmc2_nand.h> 21 #include <drivers/st/stm32_gpio.h> 22 #include <drivers/st/stm32mp_reset.h> 23 #include <lib/mmio.h> 24 #include <lib/utils_def.h> 25 26 /* Timeout for device interface reset */ 27 #define TIMEOUT_US_1_MS 1000U 28 29 /* FMC2 Compatibility */ 30 #define DT_FMC2_EBI_COMPAT "st,stm32mp1-fmc2-ebi" 31 #define DT_FMC2_NFC_COMPAT "st,stm32mp1-fmc2-nfc" 32 #define MAX_CS 2U 33 #define MAX_BANK 5U 34 35 /* FMC2 Controller Registers */ 36 #define FMC2_BCR1 0x00U 37 #define FMC2_PCR 0x80U 38 #define FMC2_SR 0x84U 39 #define FMC2_PMEM 0x88U 40 #define FMC2_PATT 0x8CU 41 #define FMC2_HECCR 0x94U 42 #define FMC2_BCHISR 0x254U 43 #define FMC2_BCHICR 0x258U 44 #define FMC2_BCHDSR0 0x27CU 45 #define FMC2_BCHDSR1 0x280U 46 #define FMC2_BCHDSR2 0x284U 47 #define FMC2_BCHDSR3 0x288U 48 #define FMC2_BCHDSR4 0x28CU 49 50 /* FMC2_BCR1 register */ 51 #define FMC2_BCR1_FMC2EN BIT(31) 52 /* FMC2_PCR register */ 53 #define FMC2_PCR_PWAITEN BIT(1) 54 #define FMC2_PCR_PBKEN BIT(2) 55 #define FMC2_PCR_PWID_MASK GENMASK_32(5, 4) 56 #define FMC2_PCR_PWID(x) (((x) << 4) & FMC2_PCR_PWID_MASK) 57 #define FMC2_PCR_PWID_8 0x0U 58 #define FMC2_PCR_PWID_16 0x1U 59 #define FMC2_PCR_ECCEN BIT(6) 60 #define FMC2_PCR_ECCALG BIT(8) 61 #define FMC2_PCR_TCLR_MASK GENMASK_32(12, 9) 62 #define FMC2_PCR_TCLR(x) (((x) << 9) & FMC2_PCR_TCLR_MASK) 63 #define FMC2_PCR_TCLR_DEFAULT 0xFU 64 #define FMC2_PCR_TAR_MASK GENMASK_32(16, 13) 65 #define FMC2_PCR_TAR(x) (((x) << 13) & FMC2_PCR_TAR_MASK) 66 #define FMC2_PCR_TAR_DEFAULT 0xFU 67 #define FMC2_PCR_ECCSS_MASK GENMASK_32(19, 17) 68 #define FMC2_PCR_ECCSS(x) (((x) << 17) & FMC2_PCR_ECCSS_MASK) 69 #define FMC2_PCR_ECCSS_512 0x1U 70 #define FMC2_PCR_ECCSS_2048 0x3U 71 #define FMC2_PCR_BCHECC BIT(24) 72 #define FMC2_PCR_WEN BIT(25) 73 /* FMC2_SR register */ 74 #define FMC2_SR_NWRF BIT(6) 75 /* FMC2_PMEM register*/ 76 #define FMC2_PMEM_MEMSET(x) (((x) & GENMASK_32(7, 0)) << 0) 77 #define FMC2_PMEM_MEMWAIT(x) (((x) & GENMASK_32(7, 0)) << 8) 78 #define FMC2_PMEM_MEMHOLD(x) (((x) & GENMASK_32(7, 0)) << 16) 79 #define FMC2_PMEM_MEMHIZ(x) (((x) & GENMASK_32(7, 0)) << 24) 80 #define FMC2_PMEM_DEFAULT 0x0A0A0A0AU 81 /* FMC2_PATT register */ 82 #define FMC2_PATT_ATTSET(x) (((x) & GENMASK_32(7, 0)) << 0) 83 #define FMC2_PATT_ATTWAIT(x) (((x) & GENMASK_32(7, 0)) << 8) 84 #define FMC2_PATT_ATTHOLD(x) (((x) & GENMASK_32(7, 0)) << 16) 85 #define FMC2_PATT_ATTHIZ(x) (((x) & GENMASK_32(7, 0)) << 24) 86 #define FMC2_PATT_DEFAULT 0x0A0A0A0AU 87 /* FMC2_BCHISR register */ 88 #define FMC2_BCHISR_DERF BIT(1) 89 /* FMC2_BCHICR register */ 90 #define FMC2_BCHICR_CLEAR_IRQ GENMASK_32(4, 0) 91 /* FMC2_BCHDSR0 register */ 92 #define FMC2_BCHDSR0_DUE BIT(0) 93 #define FMC2_BCHDSR0_DEF BIT(1) 94 #define FMC2_BCHDSR0_DEN_MASK GENMASK_32(7, 4) 95 #define FMC2_BCHDSR0_DEN_SHIFT 4U 96 /* FMC2_BCHDSR1 register */ 97 #define FMC2_BCHDSR1_EBP1_MASK GENMASK_32(12, 0) 98 #define FMC2_BCHDSR1_EBP2_MASK GENMASK_32(28, 16) 99 #define FMC2_BCHDSR1_EBP2_SHIFT 16U 100 /* FMC2_BCHDSR2 register */ 101 #define FMC2_BCHDSR2_EBP3_MASK GENMASK_32(12, 0) 102 #define FMC2_BCHDSR2_EBP4_MASK GENMASK_32(28, 16) 103 #define FMC2_BCHDSR2_EBP4_SHIFT 16U 104 /* FMC2_BCHDSR3 register */ 105 #define FMC2_BCHDSR3_EBP5_MASK GENMASK_32(12, 0) 106 #define FMC2_BCHDSR3_EBP6_MASK GENMASK_32(28, 16) 107 #define FMC2_BCHDSR3_EBP6_SHIFT 16U 108 /* FMC2_BCHDSR4 register */ 109 #define FMC2_BCHDSR4_EBP7_MASK GENMASK_32(12, 0) 110 #define FMC2_BCHDSR4_EBP8_MASK GENMASK_32(28, 16) 111 #define FMC2_BCHDSR4_EBP8_SHIFT 16U 112 113 /* Timings */ 114 #define FMC2_THIZ 0x01U 115 #define FMC2_TIO 8000U 116 #define FMC2_TSYNC 3000U 117 #define FMC2_PCR_TIMING_MASK GENMASK_32(3, 0) 118 #define FMC2_PMEM_PATT_TIMING_MASK GENMASK_32(7, 0) 119 120 #define FMC2_BBM_LEN 2U 121 #define FMC2_MAX_ECC_BYTES 14U 122 #define TIMEOUT_US_10_MS 10000U 123 #define FMC2_PSEC_PER_MSEC (1000UL * 1000UL * 1000UL) 124 125 enum stm32_fmc2_ecc { 126 FMC2_ECC_HAM = 1U, 127 FMC2_ECC_BCH4 = 4U, 128 FMC2_ECC_BCH8 = 8U 129 }; 130 131 struct stm32_fmc2_cs_reg { 132 uintptr_t data_base; 133 uintptr_t cmd_base; 134 uintptr_t addr_base; 135 }; 136 137 struct stm32_fmc2_nand_timings { 138 uint8_t tclr; 139 uint8_t tar; 140 uint8_t thiz; 141 uint8_t twait; 142 uint8_t thold_mem; 143 uint8_t tset_mem; 144 uint8_t thold_att; 145 uint8_t tset_att; 146 }; 147 148 struct stm32_fmc2_nfc { 149 uintptr_t reg_base; 150 struct stm32_fmc2_cs_reg cs[MAX_CS]; 151 unsigned long clock_id; 152 unsigned int reset_id; 153 uint8_t cs_sel; 154 }; 155 156 static struct stm32_fmc2_nfc stm32_fmc2; 157 158 static uintptr_t fmc2_base(void) 159 { 160 return stm32_fmc2.reg_base; 161 } 162 163 static void stm32_fmc2_nand_setup_timing(void) 164 { 165 struct stm32_fmc2_nand_timings tims; 166 unsigned long hclk = clk_get_rate(stm32_fmc2.clock_id); 167 unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U); 168 unsigned long timing, tar, tclr, thiz, twait; 169 unsigned long tset_mem, tset_att, thold_mem, thold_att; 170 uint32_t pcr, pmem, patt; 171 172 tar = MAX(hclkp, NAND_TAR_MIN); 173 timing = div_round_up(tar, hclkp) - 1U; 174 tims.tar = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); 175 176 tclr = MAX(hclkp, NAND_TCLR_MIN); 177 timing = div_round_up(tclr, hclkp) - 1U; 178 tims.tclr = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK); 179 180 tims.thiz = FMC2_THIZ; 181 thiz = (tims.thiz + 1U) * hclkp; 182 183 /* 184 * tWAIT > tRP 185 * tWAIT > tWP 186 * tWAIT > tREA + tIO 187 */ 188 twait = MAX(hclkp, NAND_TRP_MIN); 189 twait = MAX(twait, NAND_TWP_MIN); 190 twait = MAX(twait, NAND_TREA_MAX + FMC2_TIO); 191 timing = div_round_up(twait, hclkp); 192 tims.twait = CLAMP(timing, 1UL, 193 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 194 195 /* 196 * tSETUP_MEM > tCS - tWAIT 197 * tSETUP_MEM > tALS - tWAIT 198 * tSETUP_MEM > tDS - (tWAIT - tHIZ) 199 */ 200 tset_mem = hclkp; 201 if ((twait < NAND_TCS_MIN) && (tset_mem < (NAND_TCS_MIN - twait))) { 202 tset_mem = NAND_TCS_MIN - twait; 203 } 204 if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) && 205 (tset_mem < (NAND_TDS_MIN - (twait - thiz)))) { 206 tset_mem = NAND_TDS_MIN - (twait - thiz); 207 } 208 timing = div_round_up(tset_mem, hclkp); 209 tims.tset_mem = CLAMP(timing, 1UL, 210 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 211 212 /* 213 * tHOLD_MEM > tCH 214 * tHOLD_MEM > tREH - tSETUP_MEM 215 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) 216 */ 217 thold_mem = MAX(hclkp, NAND_TCH_MIN); 218 if ((tset_mem < NAND_TREH_MIN) && 219 (thold_mem < (NAND_TREH_MIN - tset_mem))) { 220 thold_mem = NAND_TREH_MIN - tset_mem; 221 } 222 if (((tset_mem + twait) < NAND_TRC_MIN) && 223 (thold_mem < (NAND_TRC_MIN - (tset_mem + twait)))) { 224 thold_mem = NAND_TRC_MIN - (tset_mem + twait); 225 } 226 if (((tset_mem + twait) < NAND_TWC_MIN) && 227 (thold_mem < (NAND_TWC_MIN - (tset_mem + twait)))) { 228 thold_mem = NAND_TWC_MIN - (tset_mem + twait); 229 } 230 timing = div_round_up(thold_mem, hclkp); 231 tims.thold_mem = CLAMP(timing, 1UL, 232 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 233 234 /* 235 * tSETUP_ATT > tCS - tWAIT 236 * tSETUP_ATT > tCLS - tWAIT 237 * tSETUP_ATT > tALS - tWAIT 238 * tSETUP_ATT > tRHW - tHOLD_MEM 239 * tSETUP_ATT > tDS - (tWAIT - tHIZ) 240 */ 241 tset_att = hclkp; 242 if ((twait < NAND_TCS_MIN) && (tset_att < (NAND_TCS_MIN - twait))) { 243 tset_att = NAND_TCS_MIN - twait; 244 } 245 if ((thold_mem < NAND_TRHW_MIN) && 246 (tset_att < (NAND_TRHW_MIN - thold_mem))) { 247 tset_att = NAND_TRHW_MIN - thold_mem; 248 } 249 if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) && 250 (tset_att < (NAND_TDS_MIN - (twait - thiz)))) { 251 tset_att = NAND_TDS_MIN - (twait - thiz); 252 } 253 timing = div_round_up(tset_att, hclkp); 254 tims.tset_att = CLAMP(timing, 1UL, 255 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 256 257 /* 258 * tHOLD_ATT > tALH 259 * tHOLD_ATT > tCH 260 * tHOLD_ATT > tCLH 261 * tHOLD_ATT > tCOH 262 * tHOLD_ATT > tDH 263 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM 264 * tHOLD_ATT > tADL - tSETUP_MEM 265 * tHOLD_ATT > tWH - tSETUP_MEM 266 * tHOLD_ATT > tWHR - tSETUP_MEM 267 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) 268 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) 269 */ 270 thold_att = MAX(hclkp, NAND_TALH_MIN); 271 thold_att = MAX(thold_att, NAND_TCH_MIN); 272 thold_att = MAX(thold_att, NAND_TCLH_MIN); 273 thold_att = MAX(thold_att, NAND_TCOH_MIN); 274 thold_att = MAX(thold_att, NAND_TDH_MIN); 275 if (((NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC) > tset_mem) && 276 (thold_att < (NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem))) { 277 thold_att = NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem; 278 } 279 if ((tset_mem < NAND_TADL_MIN) && 280 (thold_att < (NAND_TADL_MIN - tset_mem))) { 281 thold_att = NAND_TADL_MIN - tset_mem; 282 } 283 if ((tset_mem < NAND_TWH_MIN) && 284 (thold_att < (NAND_TWH_MIN - tset_mem))) { 285 thold_att = NAND_TWH_MIN - tset_mem; 286 } 287 if ((tset_mem < NAND_TWHR_MIN) && 288 (thold_att < (NAND_TWHR_MIN - tset_mem))) { 289 thold_att = NAND_TWHR_MIN - tset_mem; 290 } 291 if (((tset_att + twait) < NAND_TRC_MIN) && 292 (thold_att < (NAND_TRC_MIN - (tset_att + twait)))) { 293 thold_att = NAND_TRC_MIN - (tset_att + twait); 294 } 295 if (((tset_att + twait) < NAND_TWC_MIN) && 296 (thold_att < (NAND_TWC_MIN - (tset_att + twait)))) { 297 thold_att = NAND_TWC_MIN - (tset_att + twait); 298 } 299 timing = div_round_up(thold_att, hclkp); 300 tims.thold_att = CLAMP(timing, 1UL, 301 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK); 302 303 VERBOSE("NAND timings: %u - %u - %u - %u - %u - %u - %u - %u\n", 304 tims.tclr, tims.tar, tims.thiz, tims.twait, 305 tims.thold_mem, tims.tset_mem, 306 tims.thold_att, tims.tset_att); 307 308 /* Set tclr/tar timings */ 309 pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 310 pcr &= ~FMC2_PCR_TCLR_MASK; 311 pcr |= FMC2_PCR_TCLR(tims.tclr); 312 pcr &= ~FMC2_PCR_TAR_MASK; 313 pcr |= FMC2_PCR_TAR(tims.tar); 314 315 /* Set tset/twait/thold/thiz timings in common bank */ 316 pmem = FMC2_PMEM_MEMSET(tims.tset_mem); 317 pmem |= FMC2_PMEM_MEMWAIT(tims.twait); 318 pmem |= FMC2_PMEM_MEMHOLD(tims.thold_mem); 319 pmem |= FMC2_PMEM_MEMHIZ(tims.thiz); 320 321 /* Set tset/twait/thold/thiz timings in attribute bank */ 322 patt = FMC2_PATT_ATTSET(tims.tset_att); 323 patt |= FMC2_PATT_ATTWAIT(tims.twait); 324 patt |= FMC2_PATT_ATTHOLD(tims.thold_att); 325 patt |= FMC2_PATT_ATTHIZ(tims.thiz); 326 327 mmio_write_32(fmc2_base() + FMC2_PCR, pcr); 328 mmio_write_32(fmc2_base() + FMC2_PMEM, pmem); 329 mmio_write_32(fmc2_base() + FMC2_PATT, patt); 330 } 331 332 static void stm32_fmc2_set_buswidth_16(bool set) 333 { 334 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_PWID_MASK, 335 (set ? FMC2_PCR_PWID(FMC2_PCR_PWID_16) : 0U)); 336 } 337 338 static void stm32_fmc2_set_ecc(bool enable) 339 { 340 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_ECCEN, 341 (enable ? FMC2_PCR_ECCEN : 0U)); 342 } 343 344 static int stm32_fmc2_ham_correct(uint8_t *buffer, uint8_t *eccbuffer, 345 uint8_t *ecc) 346 { 347 uint8_t xor_ecc_ones; 348 uint16_t xor_ecc_1b, xor_ecc_2b, xor_ecc_3b; 349 union { 350 uint32_t val; 351 uint8_t bytes[4]; 352 } xor_ecc; 353 354 /* Page size--------ECC_Code Size 355 * 256---------------22 bits LSB (ECC_CODE & 0x003FFFFF) 356 * 512---------------24 bits (ECC_CODE & 0x00FFFFFF) 357 * 1024--------------26 bits (ECC_CODE & 0x03FFFFFF) 358 * 2048--------------28 bits (ECC_CODE & 0x0FFFFFFF) 359 * 4096--------------30 bits (ECC_CODE & 0x3FFFFFFF) 360 * 8192--------------32 bits (ECC_CODE & 0xFFFFFFFF) 361 */ 362 363 /* For Page size 512, ECC_Code size 24 bits */ 364 xor_ecc_1b = ecc[0] ^ eccbuffer[0]; 365 xor_ecc_2b = ecc[1] ^ eccbuffer[1]; 366 xor_ecc_3b = ecc[2] ^ eccbuffer[2]; 367 368 xor_ecc.val = 0U; 369 xor_ecc.bytes[2] = xor_ecc_3b; 370 xor_ecc.bytes[1] = xor_ecc_2b; 371 xor_ecc.bytes[0] = xor_ecc_1b; 372 373 if (xor_ecc.val == 0U) { 374 return 0; /* No Error */ 375 } 376 377 xor_ecc_ones = __builtin_popcount(xor_ecc.val); 378 if (xor_ecc_ones < 23U) { 379 if (xor_ecc_ones == 12U) { 380 uint16_t bit_address, byte_address; 381 382 /* Correctable ERROR */ 383 bit_address = ((xor_ecc_1b >> 1) & BIT(0)) | 384 ((xor_ecc_1b >> 2) & BIT(1)) | 385 ((xor_ecc_1b >> 3) & BIT(2)); 386 387 byte_address = ((xor_ecc_1b >> 7) & BIT(0)) | 388 ((xor_ecc_2b) & BIT(1)) | 389 ((xor_ecc_2b >> 1) & BIT(2)) | 390 ((xor_ecc_2b >> 2) & BIT(3)) | 391 ((xor_ecc_2b >> 3) & BIT(4)) | 392 ((xor_ecc_3b << 4) & BIT(5)) | 393 ((xor_ecc_3b << 3) & BIT(6)) | 394 ((xor_ecc_3b << 2) & BIT(7)) | 395 ((xor_ecc_3b << 1) & BIT(8)); 396 397 /* Correct bit error in the data */ 398 buffer[byte_address] = 399 buffer[byte_address] ^ BIT(bit_address); 400 VERBOSE("Hamming: 1 ECC error corrected\n"); 401 402 return 0; 403 } 404 405 /* Non Correctable ERROR */ 406 ERROR("%s: Uncorrectable ECC Errors\n", __func__); 407 return -1; 408 } 409 410 /* ECC ERROR */ 411 ERROR("%s: Hamming correction error\n", __func__); 412 return -1; 413 } 414 415 416 static int stm32_fmc2_ham_calculate(uint8_t *buffer, uint8_t *ecc) 417 { 418 uint32_t heccr; 419 uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS); 420 421 while ((mmio_read_32(fmc2_base() + FMC2_SR) & FMC2_SR_NWRF) == 0U) { 422 if (timeout_elapsed(timeout)) { 423 return -ETIMEDOUT; 424 } 425 } 426 427 heccr = mmio_read_32(fmc2_base() + FMC2_HECCR); 428 429 ecc[0] = heccr; 430 ecc[1] = heccr >> 8; 431 ecc[2] = heccr >> 16; 432 433 /* Disable ECC */ 434 stm32_fmc2_set_ecc(false); 435 436 return 0; 437 } 438 439 static int stm32_fmc2_bch_correct(uint8_t *buffer, unsigned int eccsize) 440 { 441 uint32_t bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4; 442 uint16_t pos[8]; 443 int i, den; 444 uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS); 445 446 while ((mmio_read_32(fmc2_base() + FMC2_BCHISR) & 447 FMC2_BCHISR_DERF) == 0U) { 448 if (timeout_elapsed(timeout)) { 449 return -ETIMEDOUT; 450 } 451 } 452 453 bchdsr0 = mmio_read_32(fmc2_base() + FMC2_BCHDSR0); 454 bchdsr1 = mmio_read_32(fmc2_base() + FMC2_BCHDSR1); 455 bchdsr2 = mmio_read_32(fmc2_base() + FMC2_BCHDSR2); 456 bchdsr3 = mmio_read_32(fmc2_base() + FMC2_BCHDSR3); 457 bchdsr4 = mmio_read_32(fmc2_base() + FMC2_BCHDSR4); 458 459 /* Disable ECC */ 460 stm32_fmc2_set_ecc(false); 461 462 /* No error found */ 463 if ((bchdsr0 & FMC2_BCHDSR0_DEF) == 0U) { 464 return 0; 465 } 466 467 /* Too many errors detected */ 468 if ((bchdsr0 & FMC2_BCHDSR0_DUE) != 0U) { 469 return -EBADMSG; 470 } 471 472 pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK; 473 pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT; 474 pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK; 475 pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT; 476 pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK; 477 pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT; 478 pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK; 479 pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT; 480 481 den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT; 482 for (i = 0; i < den; i++) { 483 if (pos[i] < (eccsize * 8U)) { 484 uint8_t bitmask = BIT(pos[i] % 8U); 485 uint32_t offset = pos[i] / 8U; 486 487 *(buffer + offset) ^= bitmask; 488 } 489 } 490 491 return 0; 492 } 493 494 static void stm32_fmc2_hwctl(struct nand_device *nand) 495 { 496 stm32_fmc2_set_ecc(false); 497 498 if (nand->ecc.max_bit_corr != FMC2_ECC_HAM) { 499 mmio_clrbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_WEN); 500 mmio_write_32(fmc2_base() + FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ); 501 } 502 503 stm32_fmc2_set_ecc(true); 504 } 505 506 static int stm32_fmc2_read_page(struct nand_device *nand, 507 unsigned int page, uintptr_t buffer) 508 { 509 unsigned int eccsize = nand->ecc.size; 510 unsigned int eccbytes = nand->ecc.bytes; 511 unsigned int eccsteps = nand->page_size / eccsize; 512 uint8_t ecc_corr[FMC2_MAX_ECC_BYTES]; 513 uint8_t ecc_cal[FMC2_MAX_ECC_BYTES] = {0U}; 514 uint8_t *p; 515 unsigned int i; 516 unsigned int s; 517 int ret; 518 519 VERBOSE(">%s page %i buffer %lx\n", __func__, page, buffer); 520 521 ret = nand_read_page_cmd(page, 0U, 0U, 0U); 522 if (ret != 0) { 523 return ret; 524 } 525 526 for (s = 0U, i = nand->page_size + FMC2_BBM_LEN, p = (uint8_t *)buffer; 527 s < eccsteps; 528 s++, i += eccbytes, p += eccsize) { 529 stm32_fmc2_hwctl(nand); 530 531 /* Read the NAND page sector (512 bytes) */ 532 ret = nand_change_read_column_cmd(s * eccsize, (uintptr_t)p, 533 eccsize); 534 if (ret != 0) { 535 return ret; 536 } 537 538 if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) { 539 ret = stm32_fmc2_ham_calculate(p, ecc_cal); 540 if (ret != 0) { 541 return ret; 542 } 543 } 544 545 /* Read the corresponding ECC bytes */ 546 ret = nand_change_read_column_cmd(i, (uintptr_t)ecc_corr, 547 eccbytes); 548 if (ret != 0) { 549 return ret; 550 } 551 552 /* Correct the data */ 553 if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) { 554 ret = stm32_fmc2_ham_correct(p, ecc_corr, ecc_cal); 555 } else { 556 ret = stm32_fmc2_bch_correct(p, eccsize); 557 } 558 559 if (ret != 0) { 560 return ret; 561 } 562 } 563 564 return 0; 565 } 566 567 static void stm32_fmc2_read_data(struct nand_device *nand, 568 uint8_t *buff, unsigned int length, 569 bool use_bus8) 570 { 571 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; 572 573 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 574 stm32_fmc2_set_buswidth_16(false); 575 } 576 577 if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) { 578 *buff = mmio_read_8(data_base); 579 buff += sizeof(uint8_t); 580 length -= sizeof(uint8_t); 581 } 582 583 if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) && 584 (length >= sizeof(uint16_t))) { 585 *(uint16_t *)buff = mmio_read_16(data_base); 586 buff += sizeof(uint16_t); 587 length -= sizeof(uint16_t); 588 } 589 590 /* 32bit aligned */ 591 while (length >= sizeof(uint32_t)) { 592 *(uint32_t *)buff = mmio_read_32(data_base); 593 buff += sizeof(uint32_t); 594 length -= sizeof(uint32_t); 595 } 596 597 /* Read remaining bytes */ 598 if (length >= sizeof(uint16_t)) { 599 *(uint16_t *)buff = mmio_read_16(data_base); 600 buff += sizeof(uint16_t); 601 length -= sizeof(uint16_t); 602 } 603 604 if (length != 0U) { 605 *buff = mmio_read_8(data_base); 606 } 607 608 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 609 /* Reconfigure bus width to 16-bit */ 610 stm32_fmc2_set_buswidth_16(true); 611 } 612 } 613 614 static void stm32_fmc2_write_data(struct nand_device *nand, 615 uint8_t *buff, unsigned int length, 616 bool use_bus8) 617 { 618 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base; 619 620 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 621 /* Reconfigure bus width to 8-bit */ 622 stm32_fmc2_set_buswidth_16(false); 623 } 624 625 if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) { 626 mmio_write_8(data_base, *buff); 627 buff += sizeof(uint8_t); 628 length -= sizeof(uint8_t); 629 } 630 631 if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) && 632 (length >= sizeof(uint16_t))) { 633 mmio_write_16(data_base, *(uint16_t *)buff); 634 buff += sizeof(uint16_t); 635 length -= sizeof(uint16_t); 636 } 637 638 /* 32bits aligned */ 639 while (length >= sizeof(uint32_t)) { 640 mmio_write_32(data_base, *(uint32_t *)buff); 641 buff += sizeof(uint32_t); 642 length -= sizeof(uint32_t); 643 } 644 645 /* Read remaining bytes */ 646 if (length >= sizeof(uint16_t)) { 647 mmio_write_16(data_base, *(uint16_t *)buff); 648 buff += sizeof(uint16_t); 649 length -= sizeof(uint16_t); 650 } 651 652 if (length != 0U) { 653 mmio_write_8(data_base, *buff); 654 } 655 656 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) { 657 /* Reconfigure bus width to 16-bit */ 658 stm32_fmc2_set_buswidth_16(true); 659 } 660 } 661 662 static void stm32_fmc2_ctrl_init(void) 663 { 664 uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 665 uint32_t bcr1 = mmio_read_32(fmc2_base() + FMC2_BCR1); 666 667 /* Enable wait feature and NAND flash memory bank */ 668 pcr |= FMC2_PCR_PWAITEN; 669 pcr |= FMC2_PCR_PBKEN; 670 671 /* Set buswidth to 8 bits mode for identification */ 672 pcr &= ~FMC2_PCR_PWID_MASK; 673 674 /* ECC logic is disabled */ 675 pcr &= ~FMC2_PCR_ECCEN; 676 677 /* Default mode */ 678 pcr &= ~FMC2_PCR_ECCALG; 679 pcr &= ~FMC2_PCR_BCHECC; 680 pcr &= ~FMC2_PCR_WEN; 681 682 /* Set default ECC sector size */ 683 pcr &= ~FMC2_PCR_ECCSS_MASK; 684 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048); 685 686 /* Set default TCLR/TAR timings */ 687 pcr &= ~FMC2_PCR_TCLR_MASK; 688 pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT); 689 pcr &= ~FMC2_PCR_TAR_MASK; 690 pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT); 691 692 /* Enable FMC2 controller */ 693 bcr1 |= FMC2_BCR1_FMC2EN; 694 695 mmio_write_32(fmc2_base() + FMC2_BCR1, bcr1); 696 mmio_write_32(fmc2_base() + FMC2_PCR, pcr); 697 mmio_write_32(fmc2_base() + FMC2_PMEM, FMC2_PMEM_DEFAULT); 698 mmio_write_32(fmc2_base() + FMC2_PATT, FMC2_PATT_DEFAULT); 699 } 700 701 static int stm32_fmc2_exec(struct nand_req *req) 702 { 703 int ret = 0; 704 705 switch (req->type & NAND_REQ_MASK) { 706 case NAND_REQ_CMD: 707 VERBOSE("Write CMD %x\n", (uint8_t)req->type); 708 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base, 709 (uint8_t)req->type); 710 break; 711 case NAND_REQ_ADDR: 712 VERBOSE("Write ADDR %x\n", *(req->addr)); 713 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base, 714 *(req->addr)); 715 break; 716 case NAND_REQ_DATAIN: 717 VERBOSE("Read data\n"); 718 stm32_fmc2_read_data(req->nand, req->addr, req->length, 719 ((req->type & NAND_REQ_BUS_WIDTH_8) != 720 0U)); 721 break; 722 case NAND_REQ_DATAOUT: 723 VERBOSE("Write data\n"); 724 stm32_fmc2_write_data(req->nand, req->addr, req->length, 725 ((req->type & NAND_REQ_BUS_WIDTH_8) != 726 0U)); 727 break; 728 case NAND_REQ_WAIT: 729 VERBOSE("WAIT Ready\n"); 730 ret = nand_wait_ready(req->delay_ms); 731 break; 732 default: 733 ret = -EINVAL; 734 break; 735 }; 736 737 return ret; 738 } 739 740 static void stm32_fmc2_setup(struct nand_device *nand) 741 { 742 uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR); 743 744 /* Set buswidth */ 745 pcr &= ~FMC2_PCR_PWID_MASK; 746 if (nand->buswidth == NAND_BUS_WIDTH_16) { 747 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_16); 748 } 749 750 if (nand->ecc.mode == NAND_ECC_HW) { 751 nand->mtd_read_page = stm32_fmc2_read_page; 752 753 pcr &= ~FMC2_PCR_ECCALG; 754 pcr &= ~FMC2_PCR_BCHECC; 755 756 pcr &= ~FMC2_PCR_ECCSS_MASK; 757 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512); 758 759 switch (nand->ecc.max_bit_corr) { 760 case FMC2_ECC_HAM: 761 nand->ecc.bytes = 3; 762 break; 763 case FMC2_ECC_BCH8: 764 pcr |= FMC2_PCR_ECCALG; 765 pcr |= FMC2_PCR_BCHECC; 766 nand->ecc.bytes = 13; 767 break; 768 default: 769 /* Use FMC2 ECC BCH4 */ 770 pcr |= FMC2_PCR_ECCALG; 771 nand->ecc.bytes = 7; 772 break; 773 } 774 775 if ((nand->buswidth & NAND_BUS_WIDTH_16) != 0) { 776 nand->ecc.bytes++; 777 } 778 } 779 780 mmio_write_32(stm32_fmc2.reg_base + FMC2_PCR, pcr); 781 } 782 783 static const struct nand_ctrl_ops ctrl_ops = { 784 .setup = stm32_fmc2_setup, 785 .exec = stm32_fmc2_exec 786 }; 787 788 int stm32_fmc2_init(void) 789 { 790 int fmc_ebi_node; 791 int fmc_nfc_node; 792 int fmc_flash_node = 0; 793 int nchips = 0; 794 unsigned int i; 795 void *fdt = NULL; 796 const fdt32_t *cuint; 797 struct dt_node_info info; 798 uintptr_t bank_address[MAX_BANK] = { 0, 0, 0, 0, 0 }; 799 uint8_t bank_assigned = 0; 800 uint8_t bank; 801 int ret; 802 803 if (fdt_get_address(&fdt) == 0) { 804 return -FDT_ERR_NOTFOUND; 805 } 806 807 fmc_ebi_node = dt_get_node(&info, -1, DT_FMC2_EBI_COMPAT); 808 if (fmc_ebi_node < 0) { 809 return fmc_ebi_node; 810 } 811 812 if (info.status == DT_DISABLED) { 813 return -FDT_ERR_NOTFOUND; 814 } 815 816 stm32_fmc2.reg_base = info.base; 817 818 if ((info.clock < 0) || (info.reset < 0)) { 819 return -FDT_ERR_BADVALUE; 820 } 821 822 stm32_fmc2.clock_id = (unsigned long)info.clock; 823 stm32_fmc2.reset_id = (unsigned int)info.reset; 824 825 cuint = fdt_getprop(fdt, fmc_ebi_node, "ranges", NULL); 826 if (cuint == NULL) { 827 return -FDT_ERR_BADVALUE; 828 } 829 830 for (i = 0U; i < MAX_BANK; i++) { 831 bank = fdt32_to_cpu(*cuint); 832 if ((bank >= MAX_BANK) || ((bank_assigned & BIT(bank)) != 0U)) { 833 return -FDT_ERR_BADVALUE; 834 } 835 bank_assigned |= BIT(bank); 836 bank_address[bank] = fdt32_to_cpu(*(cuint + 2)); 837 cuint += 4; 838 } 839 840 /* Pinctrl initialization */ 841 if (dt_set_pinctrl_config(fmc_ebi_node) != 0) { 842 return -FDT_ERR_BADVALUE; 843 } 844 845 /* Parse NFC controller node */ 846 fmc_nfc_node = fdt_node_offset_by_compatible(fdt, fmc_ebi_node, 847 DT_FMC2_NFC_COMPAT); 848 if (fmc_nfc_node < 0) { 849 return fmc_nfc_node; 850 } 851 852 if (fdt_get_status(fmc_nfc_node) == DT_DISABLED) { 853 return -FDT_ERR_NOTFOUND; 854 } 855 856 cuint = fdt_getprop(fdt, fmc_nfc_node, "reg", NULL); 857 if (cuint == NULL) { 858 return -FDT_ERR_BADVALUE; 859 } 860 861 for (i = 0U; i < MAX_CS; i++) { 862 bank = fdt32_to_cpu(*cuint); 863 if (bank >= MAX_BANK) { 864 return -FDT_ERR_BADVALUE; 865 } 866 stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*(cuint + 1)) + 867 bank_address[bank]; 868 869 bank = fdt32_to_cpu(*(cuint + 3)); 870 if (bank >= MAX_BANK) { 871 return -FDT_ERR_BADVALUE; 872 } 873 stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 4)) + 874 bank_address[bank]; 875 876 bank = fdt32_to_cpu(*(cuint + 6)); 877 if (bank >= MAX_BANK) { 878 return -FDT_ERR_BADVALUE; 879 } 880 stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 7)) + 881 bank_address[bank]; 882 883 cuint += 9; 884 } 885 886 /* Parse flash nodes */ 887 fdt_for_each_subnode(fmc_flash_node, fdt, fmc_nfc_node) { 888 nchips++; 889 } 890 891 if (nchips != 1) { 892 WARN("Only one SLC NAND device supported\n"); 893 return -FDT_ERR_BADVALUE; 894 } 895 896 fdt_for_each_subnode(fmc_flash_node, fdt, fmc_nfc_node) { 897 /* Get chip select */ 898 cuint = fdt_getprop(fdt, fmc_flash_node, "reg", NULL); 899 if (cuint == NULL) { 900 WARN("Chip select not well defined\n"); 901 return -FDT_ERR_BADVALUE; 902 } 903 904 stm32_fmc2.cs_sel = fdt32_to_cpu(*cuint); 905 if (stm32_fmc2.cs_sel >= MAX_CS) { 906 return -FDT_ERR_BADVALUE; 907 } 908 909 VERBOSE("NAND CS %i\n", stm32_fmc2.cs_sel); 910 } 911 912 /* Enable Clock */ 913 clk_enable(stm32_fmc2.clock_id); 914 915 /* Reset IP */ 916 ret = stm32mp_reset_assert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS); 917 if (ret != 0) { 918 panic(); 919 } 920 ret = stm32mp_reset_deassert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS); 921 if (ret != 0) { 922 panic(); 923 } 924 925 /* Setup default IP registers */ 926 stm32_fmc2_ctrl_init(); 927 928 /* Setup default timings */ 929 stm32_fmc2_nand_setup_timing(); 930 931 /* Init NAND RAW framework */ 932 nand_raw_ctrl_init(&ctrl_ops); 933 934 return 0; 935 } 936