xref: /rk3399_ARM-atf/docs/glossary.rst (revision 1b491eead580d7849a45a38f2c6a935a5d8d1160)
1Glossary
2========
3
4This glossary provides definitions for terms and abbreviations used in the TF-A
5documentation.
6
7You can find additional definitions in the `Arm Glossary`_.
8
9.. glossary::
10   :sorted:
11
12   AArch32
13      32-bit execution state of the ARMv8 ISA
14
15   AArch64
16      64-bit execution state of the ARMv8 ISA
17
18   AMU
19      Activity Monitor Unit, a hardware monitoring unit introduced by FEAT_AMUv1
20      that exposes CPU core runtime metrics as a set of counter registers.
21
22   API
23      Application Programming Interface
24
25   AT
26      Address Translation
27
28   BTI
29      Branch Target Identification. An Armv8.5 extension providing additional
30      control flow integrity around indirect branches and their targets.
31
32   CoT
33   COT
34      Chain of Trust
35
36   CSS
37      Compute Sub-System
38
39   CVE
40      Common Vulnerabilities and Exposures. A CVE document is commonly used to
41      describe a publicly-known security vulnerability.
42
43   DCE
44      DRTM Configuration Environment
45
46   D-CRTM
47      Dynamic Code Root of Trust for Measurement
48
49   DLME
50      Dynamically Launched Measured Environment
51
52   DRTM
53      Dynamic Root of Trust for Measurement
54
55   DS-5
56      Arm Development Studio 5
57
58   DSU
59      DynamIQ Shared Unit
60
61   DT
62      Device Tree
63
64   DTB
65      Device Tree Blob
66
67   EL
68      Exception Level
69
70   EHF
71      Exception Handling Framework
72
73   FCONF
74      Firmware Configuration Framework
75
76   FDT
77      Flattened Device Tree
78
79   FF-A
80      Firmware Framework for Arm A-profile
81
82   FIP
83      Firmware Image Package
84
85   FVP
86      Fixed Virtual Platform
87
88   FWU
89      FirmWare Update
90
91   GIC
92      Generic Interrupt Controller
93
94   ISA
95      Instruction Set Architecture
96
97   Linaro
98      A collaborative engineering organization consolidating
99      and optimizing open source software and tools for the Arm architecture.
100
101   LSP
102      A logical secure partition managed by SPM
103
104   MMU
105      Memory Management Unit
106
107   MPAM
108      Memory Partitioning And Monitoring. An optional Armv8.4 extension.
109
110   MPMM
111     Maximum Power Mitigation Mechanism, an optional power management mechanism
112     supported by some Arm Armv9-A cores.
113
114   MPIDR
115      Multiprocessor Affinity Register
116
117   MTE
118      Memory Tagging Extension. An optional Armv8.5 extension that enables
119      hardware-assisted memory tagging.
120
121   OEN
122      Owning Entity Number
123
124   OP-TEE
125      Open Portable Trusted Execution Environment. An example of a :term:`TEE`
126
127   OTE
128      Open-source Trusted Execution Environment
129
130   PDD
131      Platform Design Document
132
133   PAUTH
134      Pointer Authentication. An optional extension introduced in Armv8.3.
135
136   PMF
137      Performance Measurement Framework
138
139   PSA
140      Platform Security Architecture
141
142   PSCI
143      Power State Coordination Interface
144
145   RAS
146      Reliability, Availability, and Serviceability extensions. A mandatory
147      extension for the Armv8.2 architecture and later. An optional extension to
148      the base Armv8 architecture.
149
150   ROT
151      Root of Trust
152
153   SCMI
154      System Control and Management Interface
155
156   SCP
157      System Control Processor
158
159   SDEI
160      Software Delegated Exception Interface
161
162   SDS
163      Shared Data Storage
164
165   SEA
166      Synchronous External Abort
167
168   SiP
169   SIP
170      Silicon Provider
171
172   SMC
173      Secure Monitor Call
174
175   SMCCC
176      :term:`SMC` Calling Convention
177
178   SoC
179      System on Chip
180
181   SP
182      Secure Partition
183
184   SPD
185      Secure Payload Dispatcher
186
187   SPM
188      Secure Partition Manager
189
190   SRTM
191      Static Root of Trust for Measurement
192
193   SSBS
194      Speculative Store Bypass Safe. Introduced in Armv8.5, this configuration
195      bit can be set by software to allow or prevent the hardware from
196      performing speculative operations.
197
198   SVE
199      Scalable Vector Extension
200
201   TBB
202      Trusted Board Boot
203
204   TBBR
205      Trusted Board Boot Requirements
206
207   TCB
208      Trusted Compute Base
209
210   TCG
211      Trusted Computing Group
212
213   TEE
214      Trusted Execution Environment
215
216   TF-A
217      Trusted Firmware-A
218
219   TF-M
220      Trusted Firmware-M
221
222   TLB
223      Translation Lookaside Buffer
224
225   TLK
226      Trusted Little Kernel. A Trusted OS from NVIDIA.
227
228   TPM
229      Trusted Platform Module
230
231   TRNG
232      True Random Number Generator (hardware based)
233
234   TSP
235      Test Secure Payload
236
237   TZC
238      TrustZone Controller
239
240   UBSAN
241      Undefined Behavior Sanitizer
242
243   UEFI
244      Unified Extensible Firmware Interface
245
246   WDOG
247      Watchdog
248
249   XLAT
250      Translation (abbr.). For example, "XLAT table".
251
252.. _`Arm Glossary`: https://developer.arm.com/support/arm-glossary
253