1NXP SoCs - Overview 2===================== 3.. section-numbering:: 4 :suffix: . 5 6The QorIQ family of ARM based SoCs that are supported on TF-A are: 7 81. LX2160A 9 10- SoC Overview: 11 12The LX2160A multicore processor, the highest-performance member of the 13Layerscape family, combines FinFET process technology's low power and 14sixteen Arm® Cortex®-A72 cores with datapath acceleration optimized for 15L2/3 packet processing, together with security offload, robust traffic 16management and quality of service. 17 18Details about LX2160A can be found at `lx2160a`_. 19 20- LX2160ARDB Board: 21 22The LX2160A reference design board provides a comprehensive platform 23that enables design and evaluation of the LX2160A or LX2162A processors. It 24comes preloaded with a board support package (BSP) based on a standard Linux 25kernel. 26 27Board details can be fetched from the link: `lx2160ardb`_. 28 292. LS1028A 30 31- SoC Overview: 32 33The Layerscape LS1028A applications processor for industrial and 34automotive includes a time-sensitive networking (TSN) -enabled Ethernet 35switch and Ethernet controllers to support converged IT and OT networks. 36Two powerful 64-bit Arm®v8 cores support real-time processing for 37industrial control and virtual machines for edge computing in the IoT. 38The integrated GPU and LCD controller enable Human-Machine Interface 39(HMI) systems with next-generation interfaces. 40 41Details about LS1028A can be found at `ls1028a`_. 42 43- LS1028ARDB Board: 44 45The LS1028A reference design board (RDB) is a computing, evaluation, 46and development platform that supports industrial IoT applications, human 47machine interface solutions, and industrial networking. 48 49Details about LS1028A RDB board can be found at `ls1028ardb`_. 50 513. LS1043A 52 53- SoC Overview: 54 55The Layerscape LS1043A processor is NXP's first quad-core, 64-bit Arm®-based 56processor for embedded networking. The LS1023A (two core version) and the 57LS1043A (four core version) deliver greater than 10 Gbps of performance 58in a flexible I/O package supporting fanless designs. This SoC is a 59purpose-built solution for small-form-factor networking and industrial 60applications with BOM optimizations for economic low layer PCB, lower cost 61power supply and single clock design. The new 0.9V versions of the LS1043A 62and LS1023A deliver addition power savings for applications such as Wireless 63LAN and to Power over Ethernet systems. 64 65Details about LS1043A can be found at `ls1043a`_. 66 67- LS1043ARDB Board: 68 69The LS1043A reference design board (RDB) is a computing, evaluation, and 70development platform that supports the Layerscape LS1043A architecture 71processor. The LS1043A-RDB can help shorten your time to market by providing 72the following features: 73 74Memory subsystem: 75 * 2GByte DDR4 SDRAM (32bit bus) 76 * 128 Mbyte NOR flash single-chip memory 77 * 512 Mbyte NAND flash 78 * 16 Mbyte high-speed SPI flash 79 * SD connector to interface with the SD memory card 80 81Ethernet: 82 * XFI 10G port 83 * QSGMII with 4x 1G ports 84 * Two RGMII ports 85 86PCIe: 87 * PCIe2 (Lanes C) to mini-PCIe slot 88 * PCIe3 (Lanes D) to PCIe slot 89 90USB 3.0: two super speed USB 3.0 type A ports 91 92UART: supports two UARTs up to 115200 bps for console 93 94Details about LS1043A RDB board can be found at `ls1043ardb`_. 95 96Table of supported boot-modes by each platform & platform that needs FIP-DDR: 97----------------------------------------------------------------------------- 98 99+---------------------+---------------------------------------------------------------------+-----------------+ 100| | BOOT_MODE | | 101| PLAT +-------+--------+-------+-------+-------+-------------+--------------+ fip_ddr_needed | 102| | sd | qspi | nor | nand | emmc | flexspi_nor | flexspi_nand | | 103+=====================+=======+========+=======+=======+=======+=============+==============+=================+ 104| lx2160ardb | yes | | | | yes | yes | | yes | 105+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ 106| ls1028ardb | yes | | | | yes | yes | | no | 107+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ 108| ls1043ardb | yes | | yes | yes | | | | no | 109+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ 110 111 112Boot Sequence 113------------- 114:: 115 116+ Secure World | Normal World 117+ EL0 | 118+ | 119+ EL1 BL32(Tee OS) | kernel 120+ ^ | | ^ 121+ | | | | 122+ EL2 | | | BL33(u-boot) 123+ | | | ^ 124+ | v | / 125+ EL3 BootROM --> BL2 --> BL31 ---------------/ 126+ 127 128Boot Sequence with FIP-DDR 129-------------------------- 130:: 131 132+ Secure World | Normal World 133+ EL0 | 134+ | 135+ EL1 fip-ddr BL32(Tee OS) | kernel 136+ ^ | ^ | | ^ 137+ | | | | | | 138+ EL2 | | | | | BL33(u-boot) 139+ | | | | | ^ 140+ | v | v | / 141+ EL3 BootROM --> BL2 -----> BL31 ---------------/ 142+ 143 144DDR Memory Layout 145-------------------------- 146 147NXP Platforms divide DRAM into banks: 148 149- DRAM0 Bank: Maximum size of this bank is fixed to 2GB, DRAM0 size is defined in platform_def.h if it is less than 2GB. 150 151- DRAM1 ~ DRAMn Bank: Greater than 2GB belongs to DRAM1 and following banks, and size of DRAMn Bank varies for one platform to others. 152 153The following diagram is default DRAM0 memory layout in which secure memory is at top of DRAM0. 154 155:: 156 157 high +---------------------------------------------+ 158 | | 159 | Secure EL1 Payload Shared Memory (2 MB) | 160 | | 161 +---------------------------------------------+ 162 | | 163 | Secure Memory (64 MB) | 164 | | 165 +---------------------------------------------+ 166 | | 167 | Non Secure Memory | 168 | | 169 low +---------------------------------------------+ 170 171How to build 172============= 173 174Code Locations 175-------------- 176 177- OP-TEE: 178 `link <https://source.codeaurora.org/external/qoriq/qoriq-components/optee_os>`__ 179 180- U-Boot: 181 `link <https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot>`__ 182 183- RCW: 184 `link <https://source.codeaurora.org/external/qoriq/qoriq-components/rcw>`__ 185 186- ddr-phy-binary: Required by platforms that need fip-ddr. 187 `link <https:://github.com/NXP/ddr-phy-binary>`__ 188 189- cst: Required for TBBR. 190 `link <https:://source.codeaurora.org/external/qoriq/qoriq-components/cst>`__ 191 192Build Procedure 193--------------- 194 195- Fetch all the above repositories into local host. 196 197- Prepare AARCH64 toolchain and set the environment variable "CROSS_COMPILE". 198 199 .. code:: shell 200 201 export CROSS_COMPILE=.../bin/aarch64-linux-gnu- 202 203- Build RCW. Refer README from the respective cloned folder for more details. 204 205- Build u-boot and OPTee firstly, and get binary images: u-boot.bin and tee.bin. 206 For u-boot you can use the <platform>_tfa_defconfig for build. 207 208- Copy/clone the repo "ddr-phy-binary" to the tfa directory for platform needing ddr-fip. 209 210- Below are the steps to build TF-A images for the supported platforms. 211 212Compilation steps without BL32 213~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 214 215BUILD BL2: 216 217-To compile 218 .. code:: shell 219 220 make PLAT=$PLAT \ 221 BOOT_MODE=<platform_supported_boot_mode> \ 222 RCW=$RCW_BIN \ 223 pbl 224 225BUILD FIP: 226 227 .. code:: shell 228 229 make PLAT=$PLAT \ 230 BOOT_MODE=<platform_supported_boot_mode> \ 231 RCW=$RCW_BIN \ 232 BL33=$UBOOT_SECURE_BIN \ 233 pbl \ 234 fip 235 236Compilation steps with BL32 237~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 238 239BUILD BL2: 240 241-To compile 242 .. code:: shell 243 244 make PLAT=$PLAT \ 245 BOOT_MODE=<platform_supported_boot_mode> \ 246 RCW=$RCW_BIN \ 247 BL32=$TEE_BIN SPD=opteed\ 248 pbl 249 250BUILD FIP: 251 252 .. code:: shell 253 254 make PLAT=$PLAT \ 255 BOOT_MODE=<platform_supported_boot_mode> \ 256 RCW=$RCW_BIN \ 257 BL32=$TEE_BIN SPD=opteed\ 258 BL33=$UBOOT_SECURE_BIN \ 259 pbl \ 260 fip 261 262 263BUILD fip-ddr (Mandatory for certain platforms, refer table above): 264~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 265 266-To compile additional fip-ddr for selected platforms(Refer above table if the platform needs fip-ddr). 267 .. code:: shell 268 269 make PLAT=<platform_name> fip-ddr 270 271 272Deploy ATF Images 273================= 274 275Note: The size in the standard uboot commands for copy to nor, qspi, nand or sd 276should be modified based on the binary size of the image to be copied. 277 278- Deploy ATF images on flexspi-Nor flash Alt Bank from U-Boot prompt. 279 -- Commands to flash images for bl2_xxx.pbl and fip.bin. 280 281 .. code:: shell 282 283 tftp 82000000 $path/bl2_flexspi_nor.pbl; 284 i2c mw 66 50 20;sf probe 0:0; sf erase 0 +$filesize; sf write 0x82000000 0x0 $filesize; 285 286 tftp 82000000 $path/fip.bin; 287 i2c mw 66 50 20;sf probe 0:0; sf erase 0x100000 +$filesize; sf write 0x82000000 0x100000 $filesize; 288 289 -- Next step is valid for platform where FIP-DDR is needed. 290 291 .. code:: shell 292 293 tftp 82000000 $path/ddr_fip.bin; 294 i2c mw 66 50 20;sf probe 0:0; sf erase 0x800000 +$filesize; sf write 0x82000000 0x800000 $filesize; 295 296 -- Then reset to alternate bank to boot up ATF. 297 298 Command for lx2160A and ls1028a platforms: 299 300 .. code:: shell 301 302 qixisreset altbank; 303 304- Deploy ATF images on SD/eMMC from U-Boot prompt. 305 -- file_size_in_block_sizeof_512 = (Size_of_bytes_tftp / 512) 306 307 .. code:: shell 308 309 mmc dev <idx>; (idx = 1 for eMMC; idx = 0 for SD) 310 311 tftp 82000000 $path/bl2_<sd>_or_<emmc>.pbl; 312 mmc write 82000000 8 <file_size_in_block_sizeof_512>; 313 314 tftp 82000000 $path/fip.bin; 315 mmc write 82000000 0x800 <file_size_in_block_sizeof_512>; 316 317 -- Next step is valid for platform that needs FIP-DDR. 318 319 .. code:: shell 320 321 tftp 82000000 $path/ddr_fip.bin; 322 mmc write 82000000 0x4000 <file_size_in_block_sizeof_512>; 323 324 -- Then reset to sd/emmc to boot up ATF from sd/emmc as boot-source. 325 326 Command for lx2160A and ls1028a platforms: 327 328 .. code:: shell 329 330 qixisreset <sd or emmc>; 331 332 Command for ls1043a platform: 333 334 .. code:: shell 335 336 cpld reset <sd or emmc>; 337 338- Deploy ATF images on IFC nor flash from U-Boot prompt. 339 340 .. code:: shell 341 342 tftp 82000000 $path/bl2_nor.pbl; 343 protect off 64000000 +$filesize; erase 64000000 +$filesize; cp.b 82000000 64000000 $filesize; 344 345 tftp 82000000 $path/fip.bin; 346 protect off 64100000 +$filesize; erase 64100000 +$filesize; cp.b 82000000 64100000 $filesize; 347 348 -- Then reset to alternate bank to boot up ATF. 349 350 Command for ls1043a platform: 351 352 .. code:: shell 353 354 cpld reset altbank; 355 356- Deploy ATF images on IFC nand flash from U-Boot prompt. 357 358 .. code:: shell 359 360 tftp 82000000 $path/bl2_nand.pbl; 361 nand erase 0x0 $filesize; nand write 82000000 0x0 $filesize; 362 363 tftp 82000000 $path/fip.bin; 364 nand erase 0x100000 $filesize;nand write 82000000 0x100000 $filesize; 365 366 -- Then reset to nand flash to boot up ATF. 367 368 Command for ls1043a platform: 369 370 .. code:: shell 371 372 cpld reset nand; 373 374 375 376Trusted Board Boot: 377=================== 378 379For TBBR, the binary name changes: 380 381+-------------+--------------------------+---------+-------------------+ 382| Boot Type | BL2 | FIP | FIP-DDR | 383+=============+==========================+=========+===================+ 384| Normal Boot | bl2_<boot_mode>.pbl | fip.bin | ddr_fip.bin | 385+-------------+--------------------------+---------+-------------------+ 386| TBBR Boot | bl2_<boot_mode>_sec.pbl | fip.bin | ddr_fip_sec.bin | 387+-------------+--------------------------+---------+-------------------+ 388 389Refer `nxp-ls-tbbr.rst`_ for detailed user steps. 390 391 392.. _lx2160a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-lx2160a-lx2120a-lx2080a-processors:LX2160A 393.. _lx2160ardb: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/layerscape-lx2160a-multicore-communications-processor:LX2160A 394.. _ls1028a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1028a-applications-processor:LS1028A 395.. _ls1028ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1028a-reference-design-board:LS1028ARDB 396.. _ls1043a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1043a-and-1023a-processors:LS1043A 397.. _ls1043ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1043a-reference-design-board:LS1043A-RDB 398.. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst 399