1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV3_H 8 #define GICV3_H 9 10 /******************************************************************************* 11 * GICv3 and 3.1 miscellaneous definitions 12 ******************************************************************************/ 13 /* Interrupt group definitions */ 14 #define INTR_GROUP1S U(0) 15 #define INTR_GROUP0 U(1) 16 #define INTR_GROUP1NS U(2) 17 18 /* Interrupt IDs reported by the HPPIR and IAR registers */ 19 #define PENDING_G1S_INTID U(1020) 20 #define PENDING_G1NS_INTID U(1021) 21 22 /* Constant to categorize LPI interrupt */ 23 #define MIN_LPI_ID U(8192) 24 25 /* GICv3 can only target up to 16 PEs with SGI */ 26 #define GICV3_MAX_SGI_TARGETS U(16) 27 28 /* PPIs INTIDs 16-31 */ 29 #define MAX_PPI_ID U(31) 30 31 #if GIC_EXT_INTID 32 33 /* GICv3.1 extended PPIs INTIDs 1056-1119 */ 34 #define MIN_EPPI_ID U(1056) 35 #define MAX_EPPI_ID U(1119) 36 37 /* Total number of GICv3.1 EPPIs */ 38 #define TOTAL_EPPI_INTR_NUM (MAX_EPPI_ID - MIN_EPPI_ID + U(1)) 39 40 /* Total number of GICv3.1 PPIs and EPPIs */ 41 #define TOTAL_PRIVATE_INTR_NUM (TOTAL_PCPU_INTR_NUM + TOTAL_EPPI_INTR_NUM) 42 43 /* GICv3.1 extended SPIs INTIDs 4096 - 5119 */ 44 #define MIN_ESPI_ID U(4096) 45 #define MAX_ESPI_ID U(5119) 46 47 /* Total number of GICv3.1 ESPIs */ 48 #define TOTAL_ESPI_INTR_NUM (MAX_ESPI_ID - MIN_ESPI_ID + U(1)) 49 50 /* Total number of GICv3.1 SPIs and ESPIs */ 51 #define TOTAL_SHARED_INTR_NUM (TOTAL_SPI_INTR_NUM + TOTAL_ESPI_INTR_NUM) 52 53 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 54 #define IS_SGI_PPI(id) (((id) <= MAX_PPI_ID) || \ 55 (((id) >= MIN_EPPI_ID) && \ 56 ((id) <= MAX_EPPI_ID))) 57 58 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 59 #define IS_SPI(id) ((((id) >= MIN_SPI_ID) && \ 60 ((id) <= MAX_SPI_ID)) || \ 61 (((id) >= MIN_ESPI_ID) && \ 62 ((id) <= MAX_ESPI_ID))) 63 #else /* GICv3 */ 64 65 /* Total number of GICv3 PPIs */ 66 #define TOTAL_PRIVATE_INTR_NUM TOTAL_PCPU_INTR_NUM 67 68 /* Total number of GICv3 SPIs */ 69 #define TOTAL_SHARED_INTR_NUM TOTAL_SPI_INTR_NUM 70 71 /* SGIs: 0-15, PPIs: 16-31 */ 72 #define IS_SGI_PPI(id) ((id) <= MAX_PPI_ID) 73 74 /* SPIs: 32-1019 */ 75 #define IS_SPI(id) (((id) >= MIN_SPI_ID) && ((id) <= MAX_SPI_ID)) 76 77 #endif /* GIC_EXT_INTID */ 78 79 /******************************************************************************* 80 * GICv3 and 3.1 specific Distributor interface register offsets and constants 81 ******************************************************************************/ 82 #define GICD_TYPER2 U(0x0c) 83 #define GICD_STATUSR U(0x10) 84 #define GICD_SETSPI_NSR U(0x40) 85 #define GICD_CLRSPI_NSR U(0x48) 86 #define GICD_SETSPI_SR U(0x50) 87 #define GICD_CLRSPI_SR U(0x58) 88 #define GICD_IGRPMODR U(0xd00) 89 #define GICD_IGROUPRE U(0x1000) 90 #define GICD_ISENABLERE U(0x1200) 91 #define GICD_ICENABLERE U(0x1400) 92 #define GICD_ISPENDRE U(0x1600) 93 #define GICD_ICPENDRE U(0x1800) 94 #define GICD_ISACTIVERE U(0x1a00) 95 #define GICD_ICACTIVERE U(0x1c00) 96 #define GICD_IPRIORITYRE U(0x2000) 97 #define GICD_ICFGRE U(0x3000) 98 #define GICD_IGRPMODRE U(0x3400) 99 #define GICD_NSACRE U(0x3600) 100 /* 101 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt ID 102 * and n >= 32, making the effective offset as 0x6100 103 */ 104 #define GICD_IROUTER U(0x6000) 105 #define GICD_IROUTERE U(0x8000) 106 107 #define GICD_PIDR2_GICV3 U(0xffe8) 108 109 #define IGRPMODR_SHIFT 5 110 111 /* GICD_CTLR bit definitions */ 112 #define CTLR_ENABLE_G1NS_SHIFT 1 113 #define CTLR_ENABLE_G1S_SHIFT 2 114 #define CTLR_ARE_S_SHIFT 4 115 #define CTLR_ARE_NS_SHIFT 5 116 #define CTLR_DS_SHIFT 6 117 #define CTLR_E1NWF_SHIFT 7 118 #define GICD_CTLR_RWP_SHIFT 31 119 120 #define CTLR_ENABLE_G1NS_MASK U(0x1) 121 #define CTLR_ENABLE_G1S_MASK U(0x1) 122 #define CTLR_ARE_S_MASK U(0x1) 123 #define CTLR_ARE_NS_MASK U(0x1) 124 #define CTLR_DS_MASK U(0x1) 125 #define CTLR_E1NWF_MASK U(0x1) 126 #define GICD_CTLR_RWP_MASK U(0x1) 127 128 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT) 129 #define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT) 130 #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT) 131 #define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT) 132 #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT) 133 #define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT) 134 #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT) 135 136 /* GICD_IROUTER shifts and masks */ 137 #define IROUTER_SHIFT 0 138 #define IROUTER_IRM_SHIFT 31 139 #define IROUTER_IRM_MASK U(0x1) 140 141 #define GICV3_IRM_PE U(0) 142 #define GICV3_IRM_ANY U(1) 143 144 #define NUM_OF_DIST_REGS 30 145 146 /* GICD_TYPER shifts and masks */ 147 #define TYPER_ESPI U(1 << 8) 148 #define TYPER_DVIS U(1 << 18) 149 #define TYPER_ESPI_RANGE_MASK U(0x1f) 150 #define TYPER_ESPI_RANGE_SHIFT U(27) 151 #define TYPER_ESPI_RANGE U(TYPER_ESPI_MASK << TYPER_ESPI_SHIFT) 152 153 /******************************************************************************* 154 * Common GIC Redistributor interface registers & constants 155 ******************************************************************************/ 156 #define GICR_V4_PCPUBASE_SHIFT 0x12 157 #define GICR_V3_PCPUBASE_SHIFT 0x11 158 #define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */ 159 #define GICR_CTLR U(0x0) 160 #define GICR_IIDR U(0x04) 161 #define GICR_TYPER U(0x08) 162 #define GICR_STATUSR U(0x10) 163 #define GICR_WAKER U(0x14) 164 #define GICR_PROPBASER U(0x70) 165 #define GICR_PENDBASER U(0x78) 166 #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + U(0x80)) 167 #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + U(0x100)) 168 #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + U(0x180)) 169 #define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + U(0x200)) 170 #define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + U(0x280)) 171 #define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + U(0x300)) 172 #define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + U(0x380)) 173 #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + U(0x400)) 174 #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + U(0xc00)) 175 #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + U(0xc04)) 176 #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + U(0xd00)) 177 #define GICR_NSACR (GICR_SGIBASE_OFFSET + U(0xe00)) 178 179 #define GICR_IGROUPR GICR_IGROUPR0 180 #define GICR_ISENABLER GICR_ISENABLER0 181 #define GICR_ICENABLER GICR_ICENABLER0 182 #define GICR_ISPENDR GICR_ISPENDR0 183 #define GICR_ICPENDR GICR_ICPENDR0 184 #define GICR_ISACTIVER GICR_ISACTIVER0 185 #define GICR_ICACTIVER GICR_ICACTIVER0 186 #define GICR_ICFGR GICR_ICFGR0 187 #define GICR_IGRPMODR GICR_IGRPMODR0 188 189 /* GICR_CTLR bit definitions */ 190 #define GICR_CTLR_UWP_SHIFT 31 191 #define GICR_CTLR_UWP_MASK U(0x1) 192 #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT) 193 #define GICR_CTLR_RWP_SHIFT 3 194 #define GICR_CTLR_RWP_MASK U(0x1) 195 #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT) 196 #define GICR_CTLR_EN_LPIS_BIT BIT_32(0) 197 198 /* GICR_WAKER bit definitions */ 199 #define WAKER_CA_SHIFT 2 200 #define WAKER_PS_SHIFT 1 201 202 #define WAKER_CA_MASK U(0x1) 203 #define WAKER_PS_MASK U(0x1) 204 205 #define WAKER_CA_BIT BIT_32(WAKER_CA_SHIFT) 206 #define WAKER_PS_BIT BIT_32(WAKER_PS_SHIFT) 207 208 /* GICR_TYPER bit definitions */ 209 #define TYPER_AFF_VAL_SHIFT 32 210 #define TYPER_PROC_NUM_SHIFT 8 211 #define TYPER_LAST_SHIFT 4 212 #define TYPER_VLPI_SHIFT 1 213 214 #define TYPER_AFF_VAL_MASK U(0xffffffff) 215 #define TYPER_PROC_NUM_MASK U(0xffff) 216 #define TYPER_LAST_MASK U(0x1) 217 218 #define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT) 219 #define TYPER_VLPI_BIT BIT_32(TYPER_VLPI_SHIFT) 220 221 #define TYPER_PPI_NUM_SHIFT U(27) 222 #define TYPER_PPI_NUM_MASK U(0x1f) 223 224 /* GICR_IIDR bit definitions */ 225 #define IIDR_PRODUCT_ID_MASK U(0xff000000) 226 #define IIDR_VARIANT_MASK U(0x000f0000) 227 #define IIDR_REVISION_MASK U(0x0000f000) 228 #define IIDR_IMPLEMENTER_MASK U(0x00000fff) 229 #define IIDR_MODEL_MASK (IIDR_PRODUCT_ID_MASK | \ 230 IIDR_IMPLEMENTER_MASK) 231 232 /******************************************************************************* 233 * GICv3 and 3.1 CPU interface registers & constants 234 ******************************************************************************/ 235 /* ICC_SRE bit definitions */ 236 #define ICC_SRE_EN_BIT BIT_32(3) 237 #define ICC_SRE_DIB_BIT BIT_32(2) 238 #define ICC_SRE_DFB_BIT BIT_32(1) 239 #define ICC_SRE_SRE_BIT BIT_32(0) 240 241 /* ICC_IGRPEN1_EL3 bit definitions */ 242 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 243 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 244 245 #define IGRPEN1_EL3_ENABLE_G1NS_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT) 246 #define IGRPEN1_EL3_ENABLE_G1S_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT) 247 248 /* ICC_IGRPEN0_EL1 bit definitions */ 249 #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0 250 #define IGRPEN1_EL1_ENABLE_G0_BIT BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT) 251 252 /* ICC_HPPIR0_EL1 bit definitions */ 253 #define HPPIR0_EL1_INTID_SHIFT 0 254 #define HPPIR0_EL1_INTID_MASK U(0xffffff) 255 256 /* ICC_HPPIR1_EL1 bit definitions */ 257 #define HPPIR1_EL1_INTID_SHIFT 0 258 #define HPPIR1_EL1_INTID_MASK U(0xffffff) 259 260 /* ICC_IAR0_EL1 bit definitions */ 261 #define IAR0_EL1_INTID_SHIFT 0 262 #define IAR0_EL1_INTID_MASK U(0xffffff) 263 264 /* ICC_IAR1_EL1 bit definitions */ 265 #define IAR1_EL1_INTID_SHIFT 0 266 #define IAR1_EL1_INTID_MASK U(0xffffff) 267 268 /* ICC SGI macros */ 269 #define SGIR_TGT_MASK ULL(0xffff) 270 #define SGIR_AFF1_SHIFT 16 271 #define SGIR_INTID_SHIFT 24 272 #define SGIR_INTID_MASK ULL(0xf) 273 #define SGIR_AFF2_SHIFT 32 274 #define SGIR_IRM_SHIFT 40 275 #define SGIR_IRM_MASK ULL(0x1) 276 #define SGIR_AFF3_SHIFT 48 277 #define SGIR_AFF_MASK ULL(0xf) 278 279 #define SGIR_IRM_TO_AFF U(0) 280 281 #define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \ 282 ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \ 283 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \ 284 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \ 285 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \ 286 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \ 287 ((_tgt) & SGIR_TGT_MASK)) 288 289 /***************************************************************************** 290 * GICv3 and 3.1 ITS registers and constants 291 *****************************************************************************/ 292 #define GITS_CTLR U(0x0) 293 #define GITS_IIDR U(0x4) 294 #define GITS_TYPER U(0x8) 295 #define GITS_CBASER U(0x80) 296 #define GITS_CWRITER U(0x88) 297 #define GITS_CREADR U(0x90) 298 #define GITS_BASER U(0x100) 299 300 /* GITS_CTLR bit definitions */ 301 #define GITS_CTLR_ENABLED_BIT BIT_32(0) 302 #define GITS_CTLR_QUIESCENT_BIT BIT_32(1) 303 304 #ifndef __ASSEMBLER__ 305 306 #include <stdbool.h> 307 #include <stdint.h> 308 309 #include <arch_helpers.h> 310 #include <common/interrupt_props.h> 311 #include <drivers/arm/gic_common.h> 312 #include <lib/utils_def.h> 313 314 static inline uintptr_t gicv3_redist_size(uint64_t typer_val) 315 { 316 #if GIC_ENABLE_V4_EXTN 317 if ((typer_val & TYPER_VLPI_BIT) != 0U) { 318 return 1U << GICR_V4_PCPUBASE_SHIFT; 319 } else { 320 return 1U << GICR_V3_PCPUBASE_SHIFT; 321 } 322 #else 323 return 1U << GICR_V3_PCPUBASE_SHIFT; 324 #endif 325 } 326 327 static inline bool gicv3_is_intr_id_special_identifier(unsigned int id) 328 { 329 return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT); 330 } 331 332 /******************************************************************************* 333 * Helper GICv3 and 3.1 macros for SEL1 334 ******************************************************************************/ 335 static inline uint32_t gicv3_acknowledge_interrupt_sel1(void) 336 { 337 return (uint32_t)read_icc_iar1_el1() & IAR1_EL1_INTID_MASK; 338 } 339 340 static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void) 341 { 342 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 343 } 344 345 static inline void gicv3_end_of_interrupt_sel1(unsigned int id) 346 { 347 /* 348 * Interrupt request deassertion from peripheral to GIC happens 349 * by clearing interrupt condition by a write to the peripheral 350 * register. It is desired that the write transfer is complete 351 * before the core tries to change GIC state from 'AP/Active' to 352 * a new state on seeing 'EOI write'. 353 * Since ICC interface writes are not ordered against Device 354 * memory writes, a barrier is required to ensure the ordering. 355 * The dsb will also ensure *completion* of previous writes with 356 * DEVICE nGnRnE attribute. 357 */ 358 dsbishst(); 359 write_icc_eoir1_el1(id); 360 } 361 362 /******************************************************************************* 363 * Helper GICv3 macros for EL3 364 ******************************************************************************/ 365 static inline uint32_t gicv3_acknowledge_interrupt(void) 366 { 367 return (uint32_t)read_icc_iar0_el1() & IAR0_EL1_INTID_MASK; 368 } 369 370 static inline void gicv3_end_of_interrupt(unsigned int id) 371 { 372 /* 373 * Interrupt request deassertion from peripheral to GIC happens 374 * by clearing interrupt condition by a write to the peripheral 375 * register. It is desired that the write transfer is complete 376 * before the core tries to change GIC state from 'AP/Active' to 377 * a new state on seeing 'EOI write'. 378 * Since ICC interface writes are not ordered against Device 379 * memory writes, a barrier is required to ensure the ordering. 380 * The dsb will also ensure *completion* of previous writes with 381 * DEVICE nGnRnE attribute. 382 */ 383 dsbishst(); 384 return write_icc_eoir0_el1(id); 385 } 386 387 /* 388 * This macro returns the total number of GICD/GICR registers corresponding to 389 * the register name 390 */ 391 #define GICD_NUM_REGS(reg_name) \ 392 DIV_ROUND_UP_2EVAL(TOTAL_SHARED_INTR_NUM, (1 << reg_name##_SHIFT)) 393 394 #define GICR_NUM_REGS(reg_name) \ 395 DIV_ROUND_UP_2EVAL(TOTAL_PRIVATE_INTR_NUM, (1 << reg_name##_SHIFT)) 396 397 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 398 #define INT_ID_MASK U(0xffffff) 399 400 /******************************************************************************* 401 * This structure describes some of the implementation defined attributes of the 402 * GICv3 IP. It is used by the platform port to specify these attributes in order 403 * to initialise the GICV3 driver. The attributes are described below. 404 * 405 * The 'gicd_base' field contains the base address of the Distributor interface 406 * programmer's view. 407 * 408 * The 'gicr_base' field contains the base address of the Re-distributor 409 * interface programmer's view. 410 * 411 * The 'interrupt_props' field is a pointer to an array that enumerates secure 412 * interrupts and their properties. If this field is not NULL, both 413 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored. 414 * 415 * The 'interrupt_props_num' field contains the number of entries in the 416 * 'interrupt_props' array. If this field is non-zero, both 'g0_interrupt_num' 417 * and 'g1s_interrupt_num' are ignored. 418 * 419 * The 'rdistif_num' field contains the number of Redistributor interfaces the 420 * GIC implements. This is equal to the number of CPUs or CPU interfaces 421 * instantiated in the GIC. 422 * 423 * The 'rdistif_base_addrs' field is a pointer to an array that has an entry for 424 * storing the base address of the Redistributor interface frame of each CPU in 425 * the system. The size of the array = 'rdistif_num'. The base addresses are 426 * detected during driver initialisation. 427 * 428 * The 'mpidr_to_core_pos' field is a pointer to a hash function which the 429 * driver will use to convert an MPIDR value to a linear core index. This index 430 * will be used for accessing the 'rdistif_base_addrs' array. This is an 431 * optional field. A GICv3 implementation maps each MPIDR to a linear core index 432 * as well. This mapping can be found by reading the "Affinity Value" and 433 * "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the 434 * "Processor Numbers" are suitable to index into an array to access core 435 * specific information. If this not the case, the platform port must provide a 436 * hash function. Otherwise, the "Processor Number" field will be used to access 437 * the array elements. 438 ******************************************************************************/ 439 typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr); 440 441 typedef struct gicv3_driver_data { 442 uintptr_t gicd_base; 443 uintptr_t gicr_base; 444 const interrupt_prop_t *interrupt_props; 445 unsigned int interrupt_props_num; 446 unsigned int rdistif_num; 447 uintptr_t *rdistif_base_addrs; 448 mpidr_hash_fn mpidr_to_core_pos; 449 } gicv3_driver_data_t; 450 451 typedef struct gicv3_redist_ctx { 452 /* 64 bits registers */ 453 uint64_t gicr_propbaser; 454 uint64_t gicr_pendbaser; 455 456 /* 32 bits registers */ 457 uint32_t gicr_ctlr; 458 uint32_t gicr_igroupr[GICR_NUM_REGS(IGROUPR)]; 459 uint32_t gicr_isenabler[GICR_NUM_REGS(ISENABLER)]; 460 uint32_t gicr_ispendr[GICR_NUM_REGS(ISPENDR)]; 461 uint32_t gicr_isactiver[GICR_NUM_REGS(ISACTIVER)]; 462 uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)]; 463 uint32_t gicr_icfgr[GICR_NUM_REGS(ICFGR)]; 464 uint32_t gicr_igrpmodr[GICR_NUM_REGS(IGRPMODR)]; 465 uint32_t gicr_nsacr; 466 } gicv3_redist_ctx_t; 467 468 typedef struct gicv3_dist_ctx { 469 /* 64 bits registers */ 470 uint64_t gicd_irouter[TOTAL_SHARED_INTR_NUM]; 471 472 /* 32 bits registers */ 473 uint32_t gicd_ctlr; 474 uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)]; 475 uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)]; 476 uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)]; 477 uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)]; 478 uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)]; 479 uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)]; 480 uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)]; 481 uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)]; 482 } gicv3_dist_ctx_t; 483 484 typedef struct gicv3_its_ctx { 485 /* 64 bits registers */ 486 uint64_t gits_cbaser; 487 uint64_t gits_cwriter; 488 uint64_t gits_baser[8]; 489 490 /* 32 bits registers */ 491 uint32_t gits_ctlr; 492 } gicv3_its_ctx_t; 493 494 /******************************************************************************* 495 * GICv3 EL3 driver API 496 ******************************************************************************/ 497 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); 498 int gicv3_rdistif_probe(const uintptr_t gicr_frame); 499 void gicv3_distif_init(void); 500 void gicv3_rdistif_init(unsigned int proc_num); 501 void gicv3_rdistif_on(unsigned int proc_num); 502 void gicv3_rdistif_off(unsigned int proc_num); 503 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame); 504 void gicv3_cpuif_enable(unsigned int proc_num); 505 void gicv3_cpuif_disable(unsigned int proc_num); 506 unsigned int gicv3_get_pending_interrupt_type(void); 507 unsigned int gicv3_get_pending_interrupt_id(void); 508 unsigned int gicv3_get_interrupt_type(unsigned int id, 509 unsigned int proc_num); 510 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx); 511 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx); 512 /* 513 * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if 514 * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no 515 * implementation-defined sequence is needed at these steps, an empty function 516 * can be provided. 517 */ 518 void gicv3_distif_post_restore(unsigned int proc_num); 519 void gicv3_distif_pre_save(unsigned int proc_num); 520 void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx); 521 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx); 522 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx); 523 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx); 524 525 unsigned int gicv3_get_running_priority(void); 526 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num); 527 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num); 528 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num); 529 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 530 unsigned int priority); 531 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 532 unsigned int type); 533 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target); 534 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, 535 u_register_t mpidr); 536 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num); 537 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num); 538 unsigned int gicv3_set_pmr(unsigned int mask); 539 540 #endif /* __ASSEMBLER__ */ 541 #endif /* GICV3_H */ 542