xref: /rk3399_ARM-atf/plat/intel/soc/common/sip/socfpga_sip_fcs.c (revision f2de48cb143c20ccd7a9c141df3d34cae74049de)
1 /*
2  * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch_helpers.h>
8 #include <lib/mmio.h>
9 
10 #include "socfpga_fcs.h"
11 #include "socfpga_mailbox.h"
12 #include "socfpga_sip_svc.h"
13 
14 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size,
15 					uint32_t *mbox_error)
16 {
17 	int status;
18 	unsigned int i;
19 	unsigned int resp_len = FCS_RANDOM_WORD_SIZE;
20 	uint32_t random_data[FCS_RANDOM_WORD_SIZE] = {0U};
21 
22 	if (!is_address_in_ddr_range(addr, FCS_RANDOM_BYTE_SIZE)) {
23 		return INTEL_SIP_SMC_STATUS_REJECTED;
24 	}
25 
26 	status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_RANDOM_GEN, NULL, 0U,
27 			CMD_CASUAL, random_data, &resp_len);
28 
29 	if (status < 0) {
30 		*mbox_error = -status;
31 		return INTEL_SIP_SMC_STATUS_ERROR;
32 	}
33 
34 	if (resp_len != FCS_RANDOM_WORD_SIZE) {
35 		*mbox_error = GENERIC_RESPONSE_ERROR;
36 		return INTEL_SIP_SMC_STATUS_ERROR;
37 	}
38 
39 	*ret_size = FCS_RANDOM_BYTE_SIZE;
40 
41 	for (i = 0U; i < FCS_RANDOM_WORD_SIZE; i++) {
42 		mmio_write_32(addr, random_data[i]);
43 		addr += MBOX_WORD_BYTE;
44 	}
45 
46 	flush_dcache_range(addr - *ret_size, *ret_size);
47 
48 	return INTEL_SIP_SMC_STATUS_OK;
49 }
50 
51 uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
52 					uint32_t *send_id)
53 {
54 	int status;
55 
56 	if (!is_address_in_ddr_range(addr, size)) {
57 		return INTEL_SIP_SMC_STATUS_REJECTED;
58 	}
59 
60 	status = mailbox_send_cmd_async(send_id, MBOX_CMD_VAB_SRC_CERT,
61 				(uint32_t *)addr, size / MBOX_WORD_BYTE,
62 				CMD_DIRECT);
63 
64 	if (status < 0) {
65 		return INTEL_SIP_SMC_STATUS_ERROR;
66 	}
67 
68 	return INTEL_SIP_SMC_STATUS_OK;
69 }
70 
71 uint32_t intel_fcs_get_provision_data(uint32_t *send_id)
72 {
73 	int status;
74 
75 	status = mailbox_send_cmd_async(send_id, MBOX_FCS_GET_PROVISION,
76 				NULL, 0U, CMD_DIRECT);
77 
78 	if (status < 0) {
79 		return INTEL_SIP_SMC_STATUS_ERROR;
80 	}
81 
82 	return INTEL_SIP_SMC_STATUS_OK;
83 }
84 
85 uint32_t intel_fcs_cryption(uint32_t mode, uint32_t src_addr,
86 		uint32_t src_size, uint32_t dst_addr,
87 		uint32_t dst_size, uint32_t *send_id)
88 {
89 	int status;
90 	uint32_t cmd;
91 
92 	if (!is_address_in_ddr_range(src_addr, src_size) ||
93 		!is_address_in_ddr_range(dst_addr, dst_size)) {
94 		return INTEL_SIP_SMC_STATUS_REJECTED;
95 	}
96 
97 	fcs_crypt_payload payload = {
98 		FCS_CRYPTION_DATA_0,
99 		src_addr,
100 		src_size,
101 		dst_addr,
102 		dst_size };
103 
104 	if (mode != 0U) {
105 		cmd = MBOX_FCS_ENCRYPT_REQ;
106 	} else {
107 		cmd = MBOX_FCS_DECRYPT_REQ;
108 	}
109 
110 	status = mailbox_send_cmd_async(send_id, cmd, (uint32_t *) &payload,
111 				sizeof(fcs_crypt_payload) / MBOX_WORD_BYTE,
112 				CMD_INDIRECT);
113 	inv_dcache_range(dst_addr, dst_size);
114 
115 	if (status < 0) {
116 		return INTEL_SIP_SMC_STATUS_REJECTED;
117 	}
118 
119 	return INTEL_SIP_SMC_STATUS_OK;
120 }
121