1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <common/fdt_wrappers.h> 9 #include <drivers/arm/gicv3.h> 10 #include <drivers/arm/gic_common.h> 11 #include <lib/mmio.h> 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 #include <plat/common/platform.h> 16 #include <platform_def.h> 17 18 static const interrupt_prop_t fpga_interrupt_props[] = { 19 PLATFORM_G1S_PROPS(INTR_GROUP1S), 20 PLATFORM_G0_PROPS(INTR_GROUP0) 21 }; 22 23 static uintptr_t fpga_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 24 25 static unsigned int fpga_mpidr_to_core_pos(unsigned long mpidr) 26 { 27 return (unsigned int)plat_core_pos_by_mpidr(mpidr); 28 } 29 30 static gicv3_driver_data_t fpga_gicv3_driver_data = { 31 .interrupt_props = fpga_interrupt_props, 32 .interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props), 33 .rdistif_num = PLATFORM_CORE_COUNT, 34 .rdistif_base_addrs = fpga_rdistif_base_addrs, 35 .mpidr_to_core_pos = fpga_mpidr_to_core_pos 36 }; 37 38 void plat_fpga_gic_init(void) 39 { 40 const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE; 41 int node, ret; 42 43 node = fdt_node_offset_by_compatible(fdt, 0, "arm,gic-v3"); 44 if (node < 0) { 45 WARN("No \"arm,gic-v3\" compatible node found in DT, no GIC support.\n"); 46 return; 47 } 48 49 /* TODO: Assuming only empty "ranges;" properties up the bus path. */ 50 ret = fdt_get_reg_props_by_index(fdt, node, 0, 51 &fpga_gicv3_driver_data.gicd_base, NULL); 52 if (ret < 0) { 53 WARN("Could not read GIC distributor address from DT.\n"); 54 return; 55 } 56 57 ret = fdt_get_reg_props_by_index(fdt, node, 1, 58 &fpga_gicv3_driver_data.gicr_base, NULL); 59 if (ret < 0) { 60 WARN("Could not read GIC redistributor address from DT.\n"); 61 return; 62 } 63 64 gicv3_driver_init(&fpga_gicv3_driver_data); 65 gicv3_distif_init(); 66 gicv3_rdistif_init(plat_my_core_pos()); 67 gicv3_cpuif_enable(plat_my_core_pos()); 68 } 69 70 void fpga_pwr_gic_on_finish(void) 71 { 72 gicv3_rdistif_init(plat_my_core_pos()); 73 gicv3_cpuif_enable(plat_my_core_pos()); 74 } 75 76 void fpga_pwr_gic_off(void) 77 { 78 gicv3_cpuif_disable(plat_my_core_pos()); 79 gicv3_rdistif_off(plat_my_core_pos()); 80 } 81 82 unsigned int fpga_get_nr_gic_cores(void) 83 { 84 return gicv3_rdistif_get_number_frames(fpga_gicv3_driver_data.gicr_base); 85 } 86 87 uintptr_t fpga_get_redist_size(void) 88 { 89 uint64_t typer_val = mmio_read_64(fpga_gicv3_driver_data.gicr_base + 90 GICR_TYPER); 91 92 return gicv3_redist_size(typer_val); 93 } 94