1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/st/stm32mp_clkfunc.h> 15 #include <lib/smccc.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <services/arm_arch_svc.h> 19 20 #define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16) 21 22 uintptr_t plat_get_ns_image_entrypoint(void) 23 { 24 return BL33_BASE; 25 } 26 27 unsigned int plat_get_syscnt_freq2(void) 28 { 29 return read_cntfrq_el0(); 30 } 31 32 static uintptr_t boot_ctx_address; 33 static uint16_t boot_itf_selected; 34 35 void stm32mp_save_boot_ctx_address(uintptr_t address) 36 { 37 boot_api_context_t *boot_context = (boot_api_context_t *)address; 38 39 boot_ctx_address = address; 40 boot_itf_selected = boot_context->boot_interface_selected; 41 } 42 43 uintptr_t stm32mp_get_boot_ctx_address(void) 44 { 45 return boot_ctx_address; 46 } 47 48 uint16_t stm32mp_get_boot_itf_selected(void) 49 { 50 return boot_itf_selected; 51 } 52 53 uintptr_t stm32mp_ddrctrl_base(void) 54 { 55 return DDRCTRL_BASE; 56 } 57 58 uintptr_t stm32mp_ddrphyc_base(void) 59 { 60 return DDRPHYC_BASE; 61 } 62 63 uintptr_t stm32mp_pwr_base(void) 64 { 65 return PWR_BASE; 66 } 67 68 uintptr_t stm32mp_rcc_base(void) 69 { 70 return RCC_BASE; 71 } 72 73 bool stm32mp_lock_available(void) 74 { 75 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; 76 77 /* The spinlocks are used only when MMU and data cache are enabled */ 78 return (read_sctlr() & c_m_bits) == c_m_bits; 79 } 80 81 #if STM32MP_USE_STM32IMAGE 82 int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer) 83 { 84 uint32_t i; 85 uint32_t img_checksum = 0U; 86 87 /* 88 * Check header/payload validity: 89 * - Header magic 90 * - Header version 91 * - Payload checksum 92 */ 93 if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) { 94 ERROR("Header magic\n"); 95 return -EINVAL; 96 } 97 98 if ((header->header_version & HEADER_VERSION_MAJOR_MASK) != 99 (BOOT_API_HEADER_VERSION & HEADER_VERSION_MAJOR_MASK)) { 100 ERROR("Header version\n"); 101 return -EINVAL; 102 } 103 104 for (i = 0U; i < header->image_length; i++) { 105 img_checksum += *(uint8_t *)(buffer + i); 106 } 107 108 if (header->payload_checksum != img_checksum) { 109 ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum, 110 header->payload_checksum); 111 return -EINVAL; 112 } 113 114 return 0; 115 } 116 #endif /* STM32MP_USE_STM32IMAGE */ 117 118 int stm32mp_map_ddr_non_cacheable(void) 119 { 120 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 121 STM32MP_DDR_MAX_SIZE, 122 MT_NON_CACHEABLE | MT_RW | MT_SECURE); 123 } 124 125 int stm32mp_unmap_ddr(void) 126 { 127 return mmap_remove_dynamic_region(STM32MP_DDR_BASE, 128 STM32MP_DDR_MAX_SIZE); 129 } 130 131 /***************************************************************************** 132 * plat_is_smccc_feature_available() - This function checks whether SMCCC 133 * feature is availabile for platform. 134 * @fid: SMCCC function id 135 * 136 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 137 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 138 *****************************************************************************/ 139 int32_t plat_is_smccc_feature_available(u_register_t fid) 140 { 141 switch (fid) { 142 case SMCCC_ARCH_SOC_ID: 143 return SMC_ARCH_CALL_SUCCESS; 144 default: 145 return SMC_ARCH_CALL_NOT_SUPPORTED; 146 } 147 } 148 149 /* Get SOC version */ 150 int32_t plat_get_soc_version(void) 151 { 152 uint32_t chip_id = stm32mp_get_chip_dev_id(); 153 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID); 154 155 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); 156 } 157 158 /* Get SOC revision */ 159 int32_t plat_get_soc_revision(void) 160 { 161 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); 162 } 163