1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``BL2``: This is an optional build option which specifies the path to BL2 49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 50 built. 51 52- ``BL2U``: This is an optional build option which specifies the path to 53 BL2U image. In this case, the BL2U in TF-A will not be built. 54 55- ``BL2_AT_EL3``: This is an optional build option that enables the use of 56 BL2 at EL3 execution level. 57 58- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 59 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 60 61- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 62 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 63 the RW sections in RAM, while leaving the RO sections in place. This option 64 enable this use-case. For now, this option is only supported when BL2_AT_EL3 65 is set to '1'. 66 67- ``BL31``: This is an optional build option which specifies the path to 68 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 69 be built. 70 71- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 72 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 73 this file name will be used to save the key. 74 75- ``BL32``: This is an optional build option which specifies the path to 76 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 77 be built. 78 79- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 80 Trusted OS Extra1 image for the ``fip`` target. 81 82- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 83 Trusted OS Extra2 image for the ``fip`` target. 84 85- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 86 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 87 this file name will be used to save the key. 88 89- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 90 ``fip`` target in case TF-A BL2 is used. 91 92- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 93 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 94 this file name will be used to save the key. 95 96- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 97 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 98 If enabled, it is needed to use a compiler that supports the option 99 ``-mbranch-protection``. Selects the branch protection features to use: 100- 0: Default value turns off all types of branch protection 101- 1: Enables all types of branch protection features 102- 2: Return address signing to its standard level 103- 3: Extend the signing to include leaf functions 104- 4: Turn on branch target identification mechanism 105 106 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 107 and resulting PAuth/BTI features. 108 109 +-------+--------------+-------+-----+ 110 | Value | GCC option | PAuth | BTI | 111 +=======+==============+=======+=====+ 112 | 0 | none | N | N | 113 +-------+--------------+-------+-----+ 114 | 1 | standard | Y | Y | 115 +-------+--------------+-------+-----+ 116 | 2 | pac-ret | Y | N | 117 +-------+--------------+-------+-----+ 118 | 3 | pac-ret+leaf | Y | N | 119 +-------+--------------+-------+-----+ 120 | 4 | bti | N | Y | 121 +-------+--------------+-------+-----+ 122 123 This option defaults to 0. 124 Note that Pointer Authentication is enabled for Non-secure world 125 irrespective of the value of this option if the CPU supports it. 126 127- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 128 compilation of each build. It must be set to a C string (including quotes 129 where applicable). Defaults to a string that contains the time and date of 130 the compilation. 131 132- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 133 build to be uniquely identified. Defaults to the current git commit id. 134 135- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 136 137- ``CFLAGS``: Extra user options appended on the compiler's command line in 138 addition to the options set by the build system. 139 140- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 141 release several CPUs out of reset. It can take either 0 (several CPUs may be 142 brought up) or 1 (only one CPU will ever be brought up during cold reset). 143 Default is 0. If the platform always brings up a single CPU, there is no 144 need to distinguish between primary and secondary CPUs and the boot path can 145 be optimised. The ``plat_is_my_cpu_primary()`` and 146 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 147 to be implemented in this case. 148 149- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 150 Defaults to ``tbbr``. 151 152- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 153 register state when an unexpected exception occurs during execution of 154 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 155 this is only enabled for a debug build of the firmware. 156 157- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 158 certificate generation tool to create new keys in case no valid keys are 159 present or specified. Allowed options are '0' or '1'. Default is '1'. 160 161- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 162 the AArch32 system registers to be included when saving and restoring the 163 CPU context. The option must be set to 0 for AArch64-only platforms (that 164 is on hardware that does not implement AArch32, or at least not at EL1 and 165 higher ELs). Default value is 1. 166 167- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore 168 operations when entering/exiting an EL2 execution context. This is of primary 169 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). 170 This option must be equal to 1 (enabled) when ``SPD=spmd`` and 171 ``SPMD_SPM_AT_SEL2`` is set. 172 173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 174 registers to be included when saving and restoring the CPU context. Default 175 is 0. 176 177- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the 178 Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 179 execution context. Default value is 0. 180 181- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 182 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 183 registers to be included when saving and restoring the CPU context as 184 part of world switch. Default value is 0. 185 Note that Pointer Authentication is enabled for Non-secure world irrespective 186 of the value of this flag if the CPU supports it. 187 188- ``DEBUG``: Chooses between a debug and release build. It can take either 0 189 (release) or 1 (debug) as values. 0 is the default. 190 191- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 192 authenticated decryption algorithm to be used to decrypt firmware/s during 193 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 194 this flag is ``none`` to disable firmware decryption which is an optional 195 feature as per TBBR. 196 197- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 198 of the binary image. If set to 1, then only the ELF image is built. 199 0 is the default. 200 201- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 202 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 203 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 204 check the latest Arm ARM. 205 206- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 207 Board Boot authentication at runtime. This option is meant to be enabled only 208 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 209 flag has to be enabled. 0 is the default. 210 211- ``E``: Boolean option to make warnings into errors. Default is 1. 212 213- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 214 the normal boot flow. It must specify the entry point address of the EL3 215 payload. Please refer to the "Booting an EL3 payload" section for more 216 details. 217 218- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 219 This is an optional architectural feature available on v8.4 onwards. Some 220 v8.2 implementations also implement an AMU and this option can be used to 221 enable this feature on those systems as well. Default is 0. 222 223- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 224 (also known as group 1 counters). These are implementation-defined counters, 225 and as such require additional platform configuration. Default is 0. 226 227- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 228 allows platforms with auxiliary counters to describe them via the 229 ``HW_CONFIG`` device tree blob. Default is 0. 230 231- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 232 are compiled out. For debug builds, this option defaults to 1, and calls to 233 ``assert()`` are left in place. For release builds, this option defaults to 0 234 and calls to ``assert()`` function are compiled out. This option can be set 235 independently of ``DEBUG``. It can also be used to hide any auxiliary code 236 that is only required for the assertion and does not fit in the assertion 237 itself. 238 239- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 240 dumps or not. It is supported in both AArch64 and AArch32. However, in 241 AArch32 the format of the frame records are not defined in the AAPCS and they 242 are defined by the implementation. This implementation of backtrace only 243 supports the format used by GCC when T32 interworking is disabled. For this 244 reason enabling this option in AArch32 will force the compiler to only 245 generate A32 code. This option is enabled by default only in AArch64 debug 246 builds, but this behaviour can be overridden in each platform's Makefile or 247 in the build command line. 248 249- ``ENABLE_FEAT_AMUv1``: Boolean option to enable access to the HAFGRTR_EL2 250 (Hypervisor Activity Monitors Fine-Grained Read Trap Register) during EL2 251 to EL3 context save/restore operations. It is an optional feature available 252 on v8.4 and onwards and must be set to 1 alongside ``ENABLE_FEAT_FGT``, to 253 access the HAFGRTR_EL2 register. Defaults to ``0``. 254 255- ``ENABLE_FEAT_ECV``: Boolean option to enable support for the Enhanced Counter 256 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 257 Physical Offset register) during EL2 to EL3 context save/restore operations. 258 Its a mandatory architectural feature in Armv8.6 and defaults to ``1`` for 259 v8.6 or later CPUs. 260 261- ``ENABLE_FEAT_FGT``: Boolean option to enable support for FGT (Fine Grain Traps) 262 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 263 Read Trap Register) during EL2 to EL3 context save/restore operations. 264 Its a mandatory architectural feature in Armv8.6 and defaults to ``1`` for 265 v8.6 or later CPUs. 266 267- ``ENABLE_FEAT_HCX``: This option sets the bit SCR_EL3.HXEn in EL3 to allow 268 access to HCRX_EL2 (extended hypervisor control register) from EL2 as well as 269 adding HCRX_EL2 to the EL2 context save/restore operations. 270 271- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 272 support in GCC for TF-A. This option is currently only supported for 273 AArch64. Default is 0. 274 275- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 276 feature. MPAM is an optional Armv8.4 extension that enables various memory 277 system components and resources to define partitions; software running at 278 various ELs can assign themselves to desired partition to control their 279 performance aspects. 280 281 When this option is set to ``1``, EL3 allows lower ELs to access their own 282 MPAM registers without trapping into EL3. This option doesn't make use of 283 partitioning in EL3, however. Platform initialisation code should configure 284 and use partitions in EL3 as required. This option defaults to ``0``. 285 286- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 287 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 288 firmware to detect and limit high activity events to assist in SoC processor 289 power domain dynamic power budgeting and limit the triggering of whole-rail 290 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 291 292- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 293 allows platforms with cores supporting MPMM to describe them via the 294 ``HW_CONFIG`` device tree blob. Default is 0. 295 296- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 297 support within generic code in TF-A. This option is currently only supported 298 in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32 299 (SP_min) for AARCH32. Default is 0. 300 301- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 302 Measurement Framework(PMF). Default is 0. 303 304- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 305 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 306 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 307 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 308 software. 309 310- ``ENABLE_RME``: Boolean option to enable support for the ARMv9 Realm 311 Management Extension. Default value is 0. This is currently an experimental 312 feature. 313 314- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 315 instrumentation which injects timestamp collection points into TF-A to 316 allow runtime performance to be measured. Currently, only PSCI is 317 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 318 as well. Default is 0. 319 320- ``ENABLE_SME_FOR_NS``: Boolean option to enable Scalable Matrix Extension 321 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 322 registers so are enabled together. Using this option without 323 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 324 world to trap to EL3. SME is an optional architectural feature for AArch64 325 and TF-A support is experimental. At this time, this build option cannot be 326 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to 327 build with these options will fail. Default is 0. 328 329- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 330 Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS 331 must also be set to use this. If enabling this, the secure world MUST 332 handle context switching for SME, SVE, and FPU/SIMD registers to ensure that 333 no data is leaked to non-secure world. This is experimental. Default is 0. 334 335- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 336 extensions. This is an optional architectural feature for AArch64. 337 The default is 1 but is automatically disabled when the target architecture 338 is AArch32. 339 340- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 341 (SVE) for the Non-secure world only. SVE is an optional architectural feature 342 for AArch64. Note that when SVE is enabled for the Non-secure world, access 343 to SIMD and floating-point functionality from the Secure world is disabled by 344 default and controlled with ENABLE_SVE_FOR_SWD. 345 This is to avoid corruption of the Non-secure world data in the Z-registers 346 which are aliased by the SIMD and FP registers. The build option is not 347 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 348 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 349 1. The default is 1 but is automatically disabled when ENABLE_SME_FOR_NS=1 350 since SME encompasses SVE. At this time, this build option cannot be used on 351 systems that have SPM_MM enabled. 352 353- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 354 SVE is an optional architectural feature for AArch64. Note that this option 355 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 356 automatically disabled when the target architecture is AArch32. 357 358- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 359 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 360 default value is set to "none". "strong" is the recommended stack protection 361 level if this feature is desired. "none" disables the stack protection. For 362 all values other than "none", the ``plat_get_stack_protector_canary()`` 363 platform hook needs to be implemented. The value is passed as the last 364 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 365 366- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 367 flag depends on ``DECRYPTION_SUPPORT`` build flag. 368 369- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 370 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 371 372- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 373 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 374 on ``DECRYPTION_SUPPORT`` build flag. 375 376- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 377 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 378 build flag. 379 380- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 381 deprecated platform APIs, helper functions or drivers within Trusted 382 Firmware as error. It can take the value 1 (flag the use of deprecated 383 APIs as error) or 0. The default is 0. 384 385- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 386 targeted at EL3. When set ``0`` (default), no exceptions are expected or 387 handled at EL3, and a panic will result. This is supported only for AArch64 388 builds. 389 390- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 391 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 392 Default value is 40 (LOG_LEVEL_INFO). 393 394- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 395 injection from lower ELs, and this build option enables lower ELs to use 396 Error Records accessed via System Registers to inject faults. This is 397 applicable only to AArch64 builds. 398 399 This feature is intended for testing purposes only, and is advisable to keep 400 disabled for production images. 401 402- ``FIP_NAME``: This is an optional build option which specifies the FIP 403 filename for the ``fip`` target. Default is ``fip.bin``. 404 405- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 406 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 407 408- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 409 410 :: 411 412 0: Encryption is done with Secret Symmetric Key (SSK) which is common 413 for a class of devices. 414 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 415 unique per device. 416 417 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 418 419- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 420 tool to create certificates as per the Chain of Trust described in 421 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 422 include the certificates in the FIP and FWU_FIP. Default value is '0'. 423 424 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 425 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 426 the corresponding certificates, and to include those certificates in the 427 FIP and FWU_FIP. 428 429 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 430 images will not include support for Trusted Board Boot. The FIP will still 431 include the corresponding certificates. This FIP can be used to verify the 432 Chain of Trust on the host machine through other mechanisms. 433 434 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 435 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 436 will not include the corresponding certificates, causing a boot failure. 437 438- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 439 inherent support for specific EL3 type interrupts. Setting this build option 440 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 441 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 442 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 443 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 444 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 445 the Secure Payload interrupts needs to be synchronously handed over to Secure 446 EL1 for handling. The default value of this option is ``0``, which means the 447 Group 0 interrupts are assumed to be handled by Secure EL1. 448 449- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 450 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 451 ``0`` (default), these exceptions will be trapped in the current exception 452 level (or in EL1 if the current exception level is EL0). 453 454- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 455 software operations are required for CPUs to enter and exit coherency. 456 However, newer systems exist where CPUs' entry to and exit from coherency 457 is managed in hardware. Such systems require software to only initiate these 458 operations, and the rest is managed in hardware, minimizing active software 459 management. In such systems, this boolean option enables TF-A to carry out 460 build and run-time optimizations during boot and power management operations. 461 This option defaults to 0 and if it is enabled, then it implies 462 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 463 464 If this flag is disabled while the platform which TF-A is compiled for 465 includes cores that manage coherency in hardware, then a compilation error is 466 generated. This is based on the fact that a system cannot have, at the same 467 time, cores that manage coherency in hardware and cores that don't. In other 468 words, a platform cannot have, at the same time, cores that require 469 ``HW_ASSISTED_COHERENCY=1`` and cores that require 470 ``HW_ASSISTED_COHERENCY=0``. 471 472 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 473 translation library (xlat tables v2) must be used; version 1 of translation 474 library is not supported. 475 476- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 477 bottom, higher addresses at the top. This build flag can be set to '1' to 478 invert this behavior. Lower addresses will be printed at the top and higher 479 addresses at the bottom. 480 481- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 482 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 483 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 484 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 485 images. 486 487- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 488 used for generating the PKCS keys and subsequent signing of the certificate. 489 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 490 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 491 compliant and is retained only for compatibility. The default value of this 492 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 493 494- ``KEY_SIZE``: This build flag enables the user to select the key size for 495 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 496 depend on the chosen algorithm and the cryptographic module. 497 498 +-----------+------------------------------------+ 499 | KEY_ALG | Possible key sizes | 500 +===========+====================================+ 501 | rsa | 1024 , 2048 (default), 3072, 4096* | 502 +-----------+------------------------------------+ 503 | ecdsa | unavailable | 504 +-----------+------------------------------------+ 505 506 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 507 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 508 509- ``HASH_ALG``: This build flag enables the user to select the secure hash 510 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 511 The default value of this flag is ``sha256``. 512 513- ``LDFLAGS``: Extra user options appended to the linkers' command line in 514 addition to the one set by the build system. 515 516- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 517 output compiled into the build. This should be one of the following: 518 519 :: 520 521 0 (LOG_LEVEL_NONE) 522 10 (LOG_LEVEL_ERROR) 523 20 (LOG_LEVEL_NOTICE) 524 30 (LOG_LEVEL_WARNING) 525 40 (LOG_LEVEL_INFO) 526 50 (LOG_LEVEL_VERBOSE) 527 528 All log output up to and including the selected log level is compiled into 529 the build. The default value is 40 in debug builds and 20 in release builds. 530 531- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 532 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 533 provide trust that the code taking the measurements and recording them has 534 not been tampered with. 535 536 This option defaults to 0. 537 538- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 539 specifies the file that contains the Non-Trusted World private key in PEM 540 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 541 542- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 543 optional. It is only needed if the platform makefile specifies that it 544 is required in order to build the ``fwu_fip`` target. 545 546- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 547 contents upon world switch. It can take either 0 (don't save and restore) or 548 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 549 wants the timer registers to be saved and restored. 550 551- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 552 for the BL image. It can be either 0 (include) or 1 (remove). The default 553 value is 0. 554 555- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 556 the underlying hardware is not a full PL011 UART but a minimally compliant 557 generic UART, which is a subset of the PL011. The driver will not access 558 any register that is not part of the SBSA generic UART specification. 559 Default value is 0 (a full PL011 compliant UART is present). 560 561- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 562 must be subdirectory of any depth under ``plat/``, and must contain a 563 platform makefile named ``platform.mk``. For example, to build TF-A for the 564 Arm Juno board, select PLAT=juno. 565 566- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 567 instead of the normal boot flow. When defined, it must specify the entry 568 point address for the preloaded BL33 image. This option is incompatible with 569 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 570 over ``PRELOADED_BL33_BASE``. 571 572- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 573 vector address can be programmed or is fixed on the platform. It can take 574 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 575 programmable reset address, it is expected that a CPU will start executing 576 code directly at the right address, both on a cold and warm reset. In this 577 case, there is no need to identify the entrypoint on boot and the boot path 578 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 579 does not need to be implemented in this case. 580 581- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 582 possible for the PSCI power-state parameter: original and extended State-ID 583 formats. This flag if set to 1, configures the generic PSCI layer to use the 584 extended format. The default value of this flag is 0, which means by default 585 the original power-state format is used by the PSCI implementation. This flag 586 should be specified by the platform makefile and it governs the return value 587 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 588 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 589 set to 1 as well. 590 591- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 592 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 593 or later CPUs. 594 595 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 596 set to ``1``. 597 598 This option is disabled by default. 599 600- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 601 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 602 entrypoint) or 1 (CPU reset to BL31 entrypoint). 603 The default value is 0. 604 605- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 606 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 607 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 608 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 609 610- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 611 file that contains the ROT private key in PEM format and enforces public key 612 hash generation. If ``SAVE_KEYS=1``, this 613 file name will be used to save the key. 614 615- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 616 certificate generation tool to save the keys used to establish the Chain of 617 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 618 619- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 620 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 621 target. 622 623- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 624 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 625 this file name will be used to save the key. 626 627- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 628 optional. It is only needed if the platform makefile specifies that it 629 is required in order to build the ``fwu_fip`` target. 630 631- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 632 Delegated Exception Interface to BL31 image. This defaults to ``0``. 633 634 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 635 set to ``1``. 636 637- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 638 isolated on separate memory pages. This is a trade-off between security and 639 memory usage. See "Isolating code and read-only data on separate memory 640 pages" section in :ref:`Firmware Design`. This flag is disabled by default 641 and affects all BL images. 642 643- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 644 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 645 allocated in RAM discontiguous from the loaded firmware image. When set, the 646 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 647 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 648 sections are placed in RAM immediately following the loaded firmware image. 649 650- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 651 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 652 discontiguous from loaded firmware images. When set, the platform need to 653 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 654 flag is disabled by default and NOLOAD sections are placed in RAM immediately 655 following the loaded firmware image. 656 657- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 658 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 659 UEFI+ACPI this can provide a certain amount of OS forward compatibility 660 with newer platforms that aren't ECAM compliant. 661 662- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 663 This build option is only valid if ``ARCH=aarch64``. The value should be 664 the path to the directory containing the SPD source, relative to 665 ``services/spd/``; the directory is expected to contain a makefile called 666 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 667 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 668 cannot be enabled when the ``SPM_MM`` option is enabled. 669 670- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 671 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 672 execution in BL1 just before handing over to BL31. At this point, all 673 firmware images have been loaded in memory, and the MMU and caches are 674 turned off. Refer to the "Debugging options" section for more details. 675 676- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM 677 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 678 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 679 extension. This is the default when enabling the SPM Dispatcher. When 680 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 681 state. This latter configuration supports pre-Armv8.4 platforms (aka not 682 implementing the Armv8.4-SecEL2 extension). 683 684- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 685 Partition Manager (SPM) implementation. The default value is ``0`` 686 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 687 enabled (``SPD=spmd``). 688 689- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 690 description of secure partitions. The build system will parse this file and 691 package all secure partition blobs into the FIP. This file is not 692 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 693 694- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 695 secure interrupts (caught through the FIQ line). Platforms can enable 696 this directive if they need to handle such interruption. When enabled, 697 the FIQ are handled in monitor mode and non secure world is not allowed 698 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 699 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 700 701- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 702 Boot feature. When set to '1', BL1 and BL2 images include support to load 703 and verify the certificates and images in a FIP, and BL1 includes support 704 for the Firmware Update. The default value is '0'. Generation and inclusion 705 of certificates in the FIP and FWU_FIP depends upon the value of the 706 ``GENERATE_COT`` option. 707 708 .. warning:: 709 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 710 already exist in disk, they will be overwritten without further notice. 711 712- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 713 specifies the file that contains the Trusted World private key in PEM 714 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 715 716- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 717 synchronous, (see "Initializing a BL32 Image" section in 718 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 719 synchronous method) or 1 (BL32 is initialized using asynchronous method). 720 Default is 0. 721 722- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 723 routing model which routes non-secure interrupts asynchronously from TSP 724 to EL3 causing immediate preemption of TSP. The EL3 is responsible 725 for saving and restoring the TSP context in this routing model. The 726 default routing model (when the value is 0) is to route non-secure 727 interrupts to TSP allowing it to save its context and hand over 728 synchronously to EL3 via an SMC. 729 730 .. note:: 731 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 732 must also be set to ``1``. 733 734- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 735 linker. When the ``LINKER`` build variable points to the armlink linker, 736 this flag is enabled automatically. To enable support for armlink, platforms 737 will have to provide a scatter file for the BL image. Currently, Tegra 738 platforms use the armlink support to compile BL3-1 images. 739 740- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 741 memory region in the BL memory map or not (see "Use of Coherent memory in 742 TF-A" section in :ref:`Firmware Design`). It can take the value 1 743 (Coherent memory region is included) or 0 (Coherent memory region is 744 excluded). Default is 1. 745 746- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 747 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 748 Default is 0. 749 750- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 751 firmware configuration framework. This will move the io_policies into a 752 configuration device tree, instead of static structure in the code base. 753 754- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 755 at runtime using fconf. If this flag is enabled, COT descriptors are 756 statically captured in tb_fw_config file in the form of device tree nodes 757 and properties. Currently, COT descriptors used by BL2 are moved to the 758 device tree and COT descriptors used by BL1 are retained in the code 759 base statically. 760 761- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 762 runtime using firmware configuration framework. The platform specific SDEI 763 shared and private events configuration is retrieved from device tree rather 764 than static C structures at compile time. This is only supported if 765 SDEI_SUPPORT build flag is enabled. 766 767- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 768 and Group1 secure interrupts using the firmware configuration framework. The 769 platform specific secure interrupt property descriptor is retrieved from 770 device tree in runtime rather than depending on static C structure at compile 771 time. 772 773- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 774 This feature creates a library of functions to be placed in ROM and thus 775 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 776 is 0. 777 778- ``V``: Verbose build. If assigned anything other than 0, the build commands 779 are printed. Default is 0. 780 781- ``VERSION_STRING``: String used in the log output for each TF-A image. 782 Defaults to a string formed by concatenating the version number, build type 783 and build string. 784 785- ``W``: Warning level. Some compiler warning options of interest have been 786 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 787 each level enabling more warning options. Default is 0. 788 789- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 790 the CPU after warm boot. This is applicable for platforms which do not 791 require interconnect programming to enable cache coherency (eg: single 792 cluster platforms). If this option is enabled, then warm boot path 793 enables D-caches immediately after enabling MMU. This option defaults to 0. 794 795- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 796 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 797 default value of this flag is ``no``. Note this option must be enabled only 798 for ARM architecture greater than Armv8.5-A. 799 800- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 801 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 802 The default value of this flag is ``0``. 803 804 ``AT`` speculative errata workaround disables stage1 page table walk for 805 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 806 produces either the correct result or failure without TLB allocation. 807 808 This boolean option enables errata for all below CPUs. 809 810 +---------+--------------+-------------------------+ 811 | Errata | CPU | Workaround Define | 812 +=========+==============+=========================+ 813 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 814 +---------+--------------+-------------------------+ 815 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 816 +---------+--------------+-------------------------+ 817 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 818 +---------+--------------+-------------------------+ 819 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 820 +---------+--------------+-------------------------+ 821 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 822 +---------+--------------+-------------------------+ 823 824 .. note:: 825 This option is enabled by build only if platform sets any of above defines 826 mentioned in ’Workaround Define' column in the table. 827 If this option is enabled for the EL3 software then EL2 software also must 828 implement this workaround due to the behaviour of the errata mentioned 829 in new SDEN document which will get published soon. 830 831- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR 832 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 833 This flag is disabled by default. 834 835- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory 836 path on the host machine which is used to build certificate generation and 837 firmware encryption tool. 838 839- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 840 functions that wait for an arbitrary time length (udelay and mdelay). The 841 default value is 0. 842 843- ``ENABLE_TRBE_FOR_NS``: This flag is used to enable access of trace buffer 844 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 845 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 846 feature for AArch64. The default is 0 and it is automatically disabled when 847 the target architecture is AArch32. 848 849- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system 850 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 851 but unused). This feature is available if trace unit such as ETMv4.x, and 852 ETE(extending ETM feature) is implemented. This flag is disabled by default. 853 854- ``ENABLE_TRF_FOR_NS``: Boolean option to enable trace filter control registers 855 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 856 if FEAT_TRF is implemented. This flag is disabled by default. 857 858GICv3 driver options 859-------------------- 860 861GICv3 driver files are included using directive: 862 863``include drivers/arm/gic/v3/gicv3.mk`` 864 865The driver can be configured with the following options set in the platform 866makefile: 867 868- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 869 Enabling this option will add runtime detection support for the 870 GIC-600, so is safe to select even for a GIC500 implementation. 871 This option defaults to 0. 872 873- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 874 for GIC-600 AE. Enabling this option will introduce support to initialize 875 the FMU. Platforms should call the init function during boot to enable the 876 FMU and its safety mechanisms. This option defaults to 0. 877 878- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 879 functionality. This option defaults to 0 880 881- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 882 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 883 functions. This is required for FVP platform which need to simulate GIC save 884 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 885 886- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 887 This option defaults to 0. 888 889- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 890 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 891 892Debugging options 893----------------- 894 895To compile a debug version and make the build more verbose use 896 897.. code:: shell 898 899 make PLAT=<platform> DEBUG=1 V=1 all 900 901AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 902example DS-5) might not support this and may need an older version of DWARF 903symbols to be emitted by GCC. This can be achieved by using the 904``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 905version to 2 is recommended for DS-5 versions older than 5.16. 906 907When debugging logic problems it might also be useful to disable all compiler 908optimizations by using ``-O0``. 909 910.. warning:: 911 Using ``-O0`` could cause output images to be larger and base addresses 912 might need to be recalculated (see the **Memory layout on Arm development 913 platforms** section in the :ref:`Firmware Design`). 914 915Extra debug options can be passed to the build system by setting ``CFLAGS`` or 916``LDFLAGS``: 917 918.. code:: shell 919 920 CFLAGS='-O0 -gdwarf-2' \ 921 make PLAT=<platform> DEBUG=1 V=1 all 922 923Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 924ignored as the linker is called directly. 925 926It is also possible to introduce an infinite loop to help in debugging the 927post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 928``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 929section. In this case, the developer may take control of the target using a 930debugger when indicated by the console output. When using DS-5, the following 931commands can be used: 932 933:: 934 935 # Stop target execution 936 interrupt 937 938 # 939 # Prepare your debugging environment, e.g. set breakpoints 940 # 941 942 # Jump over the debug loop 943 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 944 945 # Resume execution 946 continue 947 948Firmware update options 949----------------------- 950 951- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 952 in defining the firmware update metadata structure. This flag is by default 953 set to '2'. 954 955- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 956 firmware bank. Each firmware bank must have the same number of images as per 957 the `PSA FW update specification`_. 958 This flag is used in defining the firmware update metadata structure. This 959 flag is by default set to '1'. 960 961- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 962 `PSA FW update specification`_. The default value is 0, and this is an 963 experimental feature. 964 PSA firmware update implementation has some limitations, such as BL2 is 965 not part of the protocol-updatable images, if BL2 needs to be updated, then 966 it should be done through another platform-defined mechanism, and it assumes 967 that the platform's hardware supports CRC32 instructions. 968 969-------------- 970 971*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* 972 973.. _DEN0115: https://developer.arm.com/docs/den0115/latest 974.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 975