1 /* 2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2021, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <drivers/synopsys/dw_mmc.h> 16 #include <drivers/ti/uart/uart_16550.h> 17 #include <lib/xlat_tables/xlat_tables.h> 18 19 #include "qspi/cadence_qspi.h" 20 #include "socfpga_emac.h" 21 #include "socfpga_handoff.h" 22 #include "socfpga_mailbox.h" 23 #include "socfpga_private.h" 24 #include "socfpga_reset_manager.h" 25 #include "socfpga_system_manager.h" 26 #include "s10_clock_manager.h" 27 #include "s10_memory_controller.h" 28 #include "s10_pinmux.h" 29 #include "wdt/watchdog.h" 30 31 static struct mmc_device_info mmc_info; 32 33 const mmap_region_t plat_stratix10_mmap[] = { 34 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 35 MT_MEMORY | MT_RW | MT_NS), 36 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 37 MT_DEVICE | MT_RW | MT_NS), 38 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 39 MT_DEVICE | MT_RW | MT_SECURE), 40 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 41 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 42 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 45 MT_DEVICE | MT_RW | MT_NS), 46 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 47 MT_DEVICE | MT_RW | MT_NS), 48 {0}, 49 }; 50 51 boot_source_type boot_source = BOOT_SOURCE; 52 53 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 54 u_register_t x2, u_register_t x4) 55 { 56 static console_t console; 57 handoff reverse_handoff_ptr; 58 59 generic_delay_timer_init(); 60 61 if (socfpga_get_handoff(&reverse_handoff_ptr)) 62 return; 63 config_pinmux(&reverse_handoff_ptr); 64 65 config_clkmgr_handoff(&reverse_handoff_ptr); 66 enable_nonsecure_access(); 67 deassert_peripheral_reset(); 68 config_hps_hs_before_warm_reset(); 69 70 watchdog_init(get_wdt_clk()); 71 72 console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, 73 &console); 74 75 socfpga_emac_init(); 76 socfpga_delay_timer_init(); 77 init_hard_memory_controller(); 78 mailbox_init(); 79 80 if (!intel_mailbox_is_fpga_not_ready()) 81 socfpga_bridges_enable(); 82 } 83 84 85 void bl2_el3_plat_arch_setup(void) 86 { 87 88 const mmap_region_t bl_regions[] = { 89 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 90 MT_MEMORY | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 92 MT_CODE | MT_SECURE), 93 MAP_REGION_FLAT(BL_RO_DATA_BASE, 94 BL_RO_DATA_END - BL_RO_DATA_BASE, 95 MT_RO_DATA | MT_SECURE), 96 #if USE_COHERENT_MEM_BAR 97 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 98 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 99 MT_DEVICE | MT_RW | MT_SECURE), 100 #endif 101 {0}, 102 }; 103 104 setup_page_tables(bl_regions, plat_stratix10_mmap); 105 106 enable_mmu_el3(0); 107 108 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 109 110 mmc_info.mmc_dev_type = MMC_IS_SD; 111 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 112 113 /* Request ownership and direct access to QSPI */ 114 mailbox_hps_qspi_enable(); 115 116 switch (boot_source) { 117 case BOOT_SOURCE_SDMMC: 118 dw_mmc_init(¶ms, &mmc_info); 119 socfpga_io_setup(boot_source); 120 break; 121 122 case BOOT_SOURCE_QSPI: 123 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 124 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 125 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 126 socfpga_io_setup(boot_source); 127 break; 128 129 default: 130 ERROR("Unsupported boot source\n"); 131 panic(); 132 break; 133 } 134 } 135 136 uint32_t get_spsr_for_bl33_entry(void) 137 { 138 unsigned long el_status; 139 unsigned int mode; 140 uint32_t spsr; 141 142 /* Figure out what mode we enter the non-secure world in */ 143 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 144 el_status &= ID_AA64PFR0_ELX_MASK; 145 146 mode = (el_status) ? MODE_EL2 : MODE_EL1; 147 148 /* 149 * TODO: Consider the possibility of specifying the SPSR in 150 * the FIP ToC and allowing the platform to have a say as 151 * well. 152 */ 153 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 154 return spsr; 155 } 156 157 158 int bl2_plat_handle_post_image_load(unsigned int image_id) 159 { 160 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 161 162 assert(bl_mem_params); 163 164 switch (image_id) { 165 case BL33_IMAGE_ID: 166 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 167 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 168 break; 169 default: 170 break; 171 } 172 173 return 0; 174 } 175 176 /******************************************************************************* 177 * Perform any BL3-1 platform setup code 178 ******************************************************************************/ 179 void bl2_platform_setup(void) 180 { 181 } 182 183