1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/clk.h> 10 #include <drivers/st/stm32_gpio.h> 11 #include <drivers/st/stm32_iwdg.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <libfdt.h> 15 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 /* Internal layout of the 32bit OTP word board_id */ 20 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 21 #define BOARD_ID_BOARD_NB_SHIFT 16 22 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 23 #define BOARD_ID_VARCPN_SHIFT 12 24 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 25 #define BOARD_ID_REVISION_SHIFT 8 26 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 27 #define BOARD_ID_VARFG_SHIFT 4 28 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 29 30 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 31 BOARD_ID_BOARD_NB_SHIFT) 32 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 33 BOARD_ID_VARCPN_SHIFT) 34 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 35 BOARD_ID_REVISION_SHIFT) 36 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 37 BOARD_ID_VARFG_SHIFT) 38 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 39 40 #if STM32MP13 41 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(30) 42 #endif 43 #if STM32MP15 44 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) 45 #endif 46 #define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00) 47 #define TAMP_BOOT_MODE_ITF_SHIFT 8 48 49 #define TAMP_BOOT_COUNTER_REG_ID U(21) 50 51 #if defined(IMAGE_BL2) 52 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 53 STM32MP_SYSRAM_SIZE, \ 54 MT_MEMORY | \ 55 MT_RW | \ 56 MT_SECURE | \ 57 MT_EXECUTE_NEVER) 58 #elif defined(IMAGE_BL32) 59 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 60 STM32MP_SEC_SYSRAM_SIZE, \ 61 MT_MEMORY | \ 62 MT_RW | \ 63 MT_SECURE | \ 64 MT_EXECUTE_NEVER) 65 66 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 67 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 68 STM32MP_NS_SYSRAM_SIZE, \ 69 MT_DEVICE | \ 70 MT_RW | \ 71 MT_NS | \ 72 MT_EXECUTE_NEVER) 73 #endif 74 75 #if STM32MP13 76 #define MAP_SRAM_ALL MAP_REGION_FLAT(SRAMS_BASE, \ 77 SRAMS_SIZE_2MB_ALIGNED, \ 78 MT_MEMORY | \ 79 MT_RW | \ 80 MT_SECURE | \ 81 MT_EXECUTE_NEVER) 82 #endif 83 84 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 85 STM32MP1_DEVICE1_SIZE, \ 86 MT_DEVICE | \ 87 MT_RW | \ 88 MT_SECURE | \ 89 MT_EXECUTE_NEVER) 90 91 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 92 STM32MP1_DEVICE2_SIZE, \ 93 MT_DEVICE | \ 94 MT_RW | \ 95 MT_SECURE | \ 96 MT_EXECUTE_NEVER) 97 98 #if defined(IMAGE_BL2) 99 static const mmap_region_t stm32mp1_mmap[] = { 100 MAP_SEC_SYSRAM, 101 #if STM32MP13 102 MAP_SRAM_ALL, 103 #endif 104 MAP_DEVICE1, 105 #if STM32MP_RAW_NAND 106 MAP_DEVICE2, 107 #endif 108 {0} 109 }; 110 #endif 111 #if defined(IMAGE_BL32) 112 static const mmap_region_t stm32mp1_mmap[] = { 113 MAP_SEC_SYSRAM, 114 MAP_NS_SYSRAM, 115 MAP_DEVICE1, 116 MAP_DEVICE2, 117 {0} 118 }; 119 #endif 120 121 void configure_mmu(void) 122 { 123 mmap_add(stm32mp1_mmap); 124 init_xlat_tables(); 125 126 enable_mmu_svc_mon(0); 127 } 128 129 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 130 { 131 #if STM32MP13 132 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 133 #endif 134 #if STM32MP15 135 if (bank == GPIO_BANK_Z) { 136 return GPIOZ_BASE; 137 } 138 139 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 140 #endif 141 142 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 143 } 144 145 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 146 { 147 #if STM32MP13 148 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 149 #endif 150 #if STM32MP15 151 if (bank == GPIO_BANK_Z) { 152 return 0; 153 } 154 155 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 156 #endif 157 158 return bank * GPIO_BANK_OFFSET; 159 } 160 161 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 162 { 163 #if STM32MP13 164 return true; 165 #endif 166 #if STM32MP15 167 if (bank == GPIO_BANK_Z) { 168 return true; 169 } 170 171 return false; 172 #endif 173 } 174 175 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 176 { 177 #if STM32MP13 178 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 179 #endif 180 #if STM32MP15 181 if (bank == GPIO_BANK_Z) { 182 return GPIOZ; 183 } 184 185 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 186 #endif 187 188 return GPIOA + (bank - GPIO_BANK_A); 189 } 190 191 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 192 { 193 switch (bank) { 194 case GPIO_BANK_A: 195 case GPIO_BANK_B: 196 case GPIO_BANK_C: 197 case GPIO_BANK_D: 198 case GPIO_BANK_E: 199 case GPIO_BANK_F: 200 case GPIO_BANK_G: 201 case GPIO_BANK_H: 202 case GPIO_BANK_I: 203 #if STM32MP15 204 case GPIO_BANK_J: 205 case GPIO_BANK_K: 206 #endif 207 return fdt_path_offset(fdt, "/soc/pin-controller"); 208 #if STM32MP15 209 case GPIO_BANK_Z: 210 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 211 #endif 212 default: 213 panic(); 214 } 215 } 216 217 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 218 /* 219 * UART Management 220 */ 221 static const uintptr_t stm32mp1_uart_addresses[8] = { 222 USART1_BASE, 223 USART2_BASE, 224 USART3_BASE, 225 UART4_BASE, 226 UART5_BASE, 227 USART6_BASE, 228 UART7_BASE, 229 UART8_BASE, 230 }; 231 232 uintptr_t get_uart_address(uint32_t instance_nb) 233 { 234 if ((instance_nb == 0U) || 235 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 236 return 0U; 237 } 238 239 return stm32mp1_uart_addresses[instance_nb - 1U]; 240 } 241 #endif 242 243 #if STM32MP_USB_PROGRAMMER 244 struct gpio_bank_pin_list { 245 uint32_t bank; 246 uint32_t pin; 247 }; 248 249 static const struct gpio_bank_pin_list gpio_list[] = { 250 { /* USART2_RX: GPIOA3 */ 251 .bank = 0U, 252 .pin = 3U, 253 }, 254 { /* USART3_RX: GPIOB12 */ 255 .bank = 1U, 256 .pin = 12U, 257 }, 258 { /* UART4_RX: GPIOB2 */ 259 .bank = 1U, 260 .pin = 2U, 261 }, 262 { /* UART5_RX: GPIOB4 */ 263 .bank = 1U, 264 .pin = 5U, 265 }, 266 { /* USART6_RX: GPIOC7 */ 267 .bank = 2U, 268 .pin = 7U, 269 }, 270 { /* UART7_RX: GPIOF6 */ 271 .bank = 5U, 272 .pin = 6U, 273 }, 274 { /* UART8_RX: GPIOE0 */ 275 .bank = 4U, 276 .pin = 0U, 277 }, 278 }; 279 280 void stm32mp1_deconfigure_uart_pins(void) 281 { 282 size_t i; 283 284 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) { 285 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin); 286 } 287 } 288 #endif 289 290 uint32_t stm32mp_get_chip_version(void) 291 { 292 #if STM32MP13 293 return stm32mp1_syscfg_get_chip_version(); 294 #endif 295 #if STM32MP15 296 uint32_t version = 0U; 297 298 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 299 INFO("Cannot get CPU version, debug disabled\n"); 300 return 0U; 301 } 302 303 return version; 304 #endif 305 } 306 307 uint32_t stm32mp_get_chip_dev_id(void) 308 { 309 #if STM32MP13 310 return stm32mp1_syscfg_get_chip_dev_id(); 311 #endif 312 #if STM32MP15 313 uint32_t dev_id; 314 315 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 316 INFO("Use default chip ID, debug disabled\n"); 317 dev_id = STM32MP1_CHIP_ID; 318 } 319 320 return dev_id; 321 #endif 322 } 323 324 static uint32_t get_part_number(void) 325 { 326 static uint32_t part_number; 327 328 if (part_number != 0U) { 329 return part_number; 330 } 331 332 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 333 panic(); 334 } 335 336 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 337 PART_NUMBER_OTP_PART_SHIFT; 338 339 part_number |= stm32mp_get_chip_dev_id() << 16; 340 341 return part_number; 342 } 343 344 #if STM32MP15 345 static uint32_t get_cpu_package(void) 346 { 347 uint32_t package; 348 349 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 350 panic(); 351 } 352 353 package = (package & PACKAGE_OTP_PKG_MASK) >> 354 PACKAGE_OTP_PKG_SHIFT; 355 356 return package; 357 } 358 #endif 359 360 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 361 { 362 char *cpu_s, *cpu_r, *pkg; 363 364 /* MPUs Part Numbers */ 365 switch (get_part_number()) { 366 #if STM32MP13 367 case STM32MP135F_PART_NB: 368 cpu_s = "135F"; 369 break; 370 case STM32MP135D_PART_NB: 371 cpu_s = "135D"; 372 break; 373 case STM32MP135C_PART_NB: 374 cpu_s = "135C"; 375 break; 376 case STM32MP135A_PART_NB: 377 cpu_s = "135A"; 378 break; 379 case STM32MP133F_PART_NB: 380 cpu_s = "133F"; 381 break; 382 case STM32MP133D_PART_NB: 383 cpu_s = "133D"; 384 break; 385 case STM32MP133C_PART_NB: 386 cpu_s = "133C"; 387 break; 388 case STM32MP133A_PART_NB: 389 cpu_s = "133A"; 390 break; 391 case STM32MP131F_PART_NB: 392 cpu_s = "131F"; 393 break; 394 case STM32MP131D_PART_NB: 395 cpu_s = "131D"; 396 break; 397 case STM32MP131C_PART_NB: 398 cpu_s = "131C"; 399 break; 400 case STM32MP131A_PART_NB: 401 cpu_s = "131A"; 402 break; 403 #endif 404 #if STM32MP15 405 case STM32MP157C_PART_NB: 406 cpu_s = "157C"; 407 break; 408 case STM32MP157A_PART_NB: 409 cpu_s = "157A"; 410 break; 411 case STM32MP153C_PART_NB: 412 cpu_s = "153C"; 413 break; 414 case STM32MP153A_PART_NB: 415 cpu_s = "153A"; 416 break; 417 case STM32MP151C_PART_NB: 418 cpu_s = "151C"; 419 break; 420 case STM32MP151A_PART_NB: 421 cpu_s = "151A"; 422 break; 423 case STM32MP157F_PART_NB: 424 cpu_s = "157F"; 425 break; 426 case STM32MP157D_PART_NB: 427 cpu_s = "157D"; 428 break; 429 case STM32MP153F_PART_NB: 430 cpu_s = "153F"; 431 break; 432 case STM32MP153D_PART_NB: 433 cpu_s = "153D"; 434 break; 435 case STM32MP151F_PART_NB: 436 cpu_s = "151F"; 437 break; 438 case STM32MP151D_PART_NB: 439 cpu_s = "151D"; 440 break; 441 #endif 442 default: 443 cpu_s = "????"; 444 break; 445 } 446 447 /* Package */ 448 #if STM32MP13 449 /* On STM32MP13, package is not present in OTP */ 450 pkg = ""; 451 #endif 452 #if STM32MP15 453 switch (get_cpu_package()) { 454 case PKG_AA_LFBGA448: 455 pkg = "AA"; 456 break; 457 case PKG_AB_LFBGA354: 458 pkg = "AB"; 459 break; 460 case PKG_AC_TFBGA361: 461 pkg = "AC"; 462 break; 463 case PKG_AD_TFBGA257: 464 pkg = "AD"; 465 break; 466 default: 467 pkg = "??"; 468 break; 469 } 470 #endif 471 472 /* REVISION */ 473 switch (stm32mp_get_chip_version()) { 474 case STM32MP1_REV_B: 475 cpu_r = "B"; 476 break; 477 case STM32MP1_REV_Z: 478 cpu_r = "Z"; 479 break; 480 default: 481 cpu_r = "?"; 482 break; 483 } 484 485 snprintf(name, STM32_SOC_NAME_SIZE, 486 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 487 } 488 489 void stm32mp_print_cpuinfo(void) 490 { 491 char name[STM32_SOC_NAME_SIZE]; 492 493 stm32mp_get_soc_name(name); 494 NOTICE("CPU: %s\n", name); 495 } 496 497 void stm32mp_print_boardinfo(void) 498 { 499 uint32_t board_id = 0; 500 501 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 502 return; 503 } 504 505 if (board_id != 0U) { 506 char rev[2]; 507 508 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 509 rev[1] = '\0'; 510 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 511 BOARD_ID2NB(board_id), 512 BOARD_ID2VARCPN(board_id), 513 BOARD_ID2VARFG(board_id), 514 rev, 515 BOARD_ID2BOM(board_id)); 516 } 517 } 518 519 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 520 bool stm32mp_is_single_core(void) 521 { 522 #if STM32MP13 523 return true; 524 #endif 525 #if STM32MP15 526 bool single_core = false; 527 528 switch (get_part_number()) { 529 case STM32MP151A_PART_NB: 530 case STM32MP151C_PART_NB: 531 case STM32MP151D_PART_NB: 532 case STM32MP151F_PART_NB: 533 single_core = true; 534 break; 535 default: 536 break; 537 } 538 539 return single_core; 540 #endif 541 } 542 543 /* Return true when device is in closed state */ 544 bool stm32mp_is_closed_device(void) 545 { 546 uint32_t value; 547 548 if (stm32_get_otp_value(CFG0_OTP, &value) != 0) { 549 return true; 550 } 551 552 #if STM32MP13 553 value = (value & CFG0_OTP_MODE_MASK) >> CFG0_OTP_MODE_SHIFT; 554 555 switch (value) { 556 case CFG0_OPEN_DEVICE: 557 return false; 558 case CFG0_CLOSED_DEVICE: 559 case CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN: 560 case CFG0_CLOSED_DEVICE_NO_JTAG: 561 return true; 562 default: 563 panic(); 564 } 565 #endif 566 #if STM32MP15 567 return (value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE; 568 #endif 569 } 570 571 /* Return true when device supports secure boot */ 572 bool stm32mp_is_auth_supported(void) 573 { 574 bool supported = false; 575 576 switch (get_part_number()) { 577 #if STM32MP13 578 case STM32MP131C_PART_NB: 579 case STM32MP131F_PART_NB: 580 case STM32MP133C_PART_NB: 581 case STM32MP133F_PART_NB: 582 case STM32MP135C_PART_NB: 583 case STM32MP135F_PART_NB: 584 #endif 585 #if STM32MP15 586 case STM32MP151C_PART_NB: 587 case STM32MP151F_PART_NB: 588 case STM32MP153C_PART_NB: 589 case STM32MP153F_PART_NB: 590 case STM32MP157C_PART_NB: 591 case STM32MP157F_PART_NB: 592 #endif 593 supported = true; 594 break; 595 default: 596 break; 597 } 598 599 return supported; 600 } 601 602 uint32_t stm32_iwdg_get_instance(uintptr_t base) 603 { 604 switch (base) { 605 case IWDG1_BASE: 606 return IWDG1_INST; 607 case IWDG2_BASE: 608 return IWDG2_INST; 609 default: 610 panic(); 611 } 612 } 613 614 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 615 { 616 uint32_t iwdg_cfg = 0U; 617 uint32_t otp_value; 618 619 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 620 panic(); 621 } 622 623 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 624 iwdg_cfg |= IWDG_HW_ENABLED; 625 } 626 627 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 628 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 629 } 630 631 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 632 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 633 } 634 635 return iwdg_cfg; 636 } 637 638 #if defined(IMAGE_BL2) 639 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 640 { 641 uint32_t otp_value; 642 uint32_t otp; 643 uint32_t result; 644 645 if (stm32_get_otp_index(HW2_OTP, &otp, NULL) != 0) { 646 panic(); 647 } 648 649 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 650 panic(); 651 } 652 653 if ((flags & IWDG_DISABLE_ON_STOP) != 0) { 654 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 655 } 656 657 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0) { 658 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 659 } 660 661 result = bsec_write_otp(otp_value, otp); 662 if (result != BSEC_OK) { 663 return result; 664 } 665 666 /* Sticky lock OTP_IWDG (read and write) */ 667 if ((bsec_set_sr_lock(otp) != BSEC_OK) || 668 (bsec_set_sw_lock(otp) != BSEC_OK)) { 669 return BSEC_LOCK_FAIL; 670 } 671 672 return BSEC_OK; 673 } 674 #endif 675 676 #if STM32MP_USE_STM32IMAGE 677 /* Get the non-secure DDR size */ 678 uint32_t stm32mp_get_ddr_ns_size(void) 679 { 680 static uint32_t ddr_ns_size; 681 uint32_t ddr_size; 682 683 if (ddr_ns_size != 0U) { 684 return ddr_ns_size; 685 } 686 687 ddr_size = dt_get_ddr_size(); 688 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 689 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 690 panic(); 691 } 692 693 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 694 695 return ddr_ns_size; 696 } 697 #endif /* STM32MP_USE_STM32IMAGE */ 698 699 void stm32_save_boot_interface(uint32_t interface, uint32_t instance) 700 { 701 uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 702 703 clk_enable(RTCAPB); 704 705 mmio_clrsetbits_32(bkpr_itf_idx, 706 TAMP_BOOT_MODE_ITF_MASK, 707 ((interface << 4) | (instance & 0xFU)) << 708 TAMP_BOOT_MODE_ITF_SHIFT); 709 710 clk_disable(RTCAPB); 711 } 712 713 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) 714 { 715 static uint32_t itf; 716 717 if (itf == 0U) { 718 uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 719 720 clk_enable(RTCAPB); 721 722 itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >> 723 TAMP_BOOT_MODE_ITF_SHIFT; 724 725 clk_disable(RTCAPB); 726 } 727 728 *interface = itf >> 4; 729 *instance = itf & 0xFU; 730 } 731 732 #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT 733 void stm32mp1_fwu_set_boot_idx(void) 734 { 735 clk_enable(RTCAPB); 736 mmio_write_32(tamp_bkpr(TAMP_BOOT_COUNTER_REG_ID), 737 plat_fwu_get_boot_idx()); 738 clk_disable(RTCAPB); 739 } 740 #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ 741