1 /* 2 * Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdbool.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <drivers/clk.h> 18 #include <drivers/st/stm32_gpio.h> 19 #include <drivers/st/stm32mp_clkfunc.h> 20 #include <lib/mmio.h> 21 #include <lib/utils_def.h> 22 23 #define DT_GPIO_BANK_SHIFT 12 24 #define DT_GPIO_BANK_MASK GENMASK(16, 12) 25 #define DT_GPIO_PIN_SHIFT 8 26 #define DT_GPIO_PIN_MASK GENMASK(11, 8) 27 #define DT_GPIO_MODE_MASK GENMASK(7, 0) 28 29 /******************************************************************************* 30 * This function gets GPIO bank node in DT. 31 * Returns node offset if status is okay in DT, else return 0 32 ******************************************************************************/ 33 static int ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) 34 { 35 int pinctrl_subnode; 36 uint32_t bank_offset = stm32_get_gpio_bank_offset(bank); 37 38 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 39 const fdt32_t *cuint; 40 41 if (fdt_getprop(fdt, pinctrl_subnode, 42 "gpio-controller", NULL) == NULL) { 43 continue; 44 } 45 46 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 47 if (cuint == NULL) { 48 continue; 49 } 50 51 if ((fdt32_to_cpu(*cuint) == bank_offset) && 52 (fdt_get_status(pinctrl_subnode) != DT_DISABLED)) { 53 return pinctrl_subnode; 54 } 55 } 56 57 return 0; 58 } 59 60 /******************************************************************************* 61 * This function gets the pin settings from DT information. 62 * When analyze and parsing is done, set the GPIO registers. 63 * Returns 0 on success and a negative FDT error code on failure. 64 ******************************************************************************/ 65 static int dt_set_gpio_config(void *fdt, int node, uint8_t status) 66 { 67 const fdt32_t *cuint, *slewrate; 68 int len; 69 int pinctrl_node; 70 uint32_t i; 71 uint32_t speed = GPIO_SPEED_LOW; 72 uint32_t pull = GPIO_NO_PULL; 73 74 cuint = fdt_getprop(fdt, node, "pinmux", &len); 75 if (cuint == NULL) { 76 return -FDT_ERR_NOTFOUND; 77 } 78 79 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 80 if (pinctrl_node < 0) { 81 return -FDT_ERR_NOTFOUND; 82 } 83 84 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 85 if (slewrate != NULL) { 86 speed = fdt32_to_cpu(*slewrate); 87 } 88 89 if (fdt_getprop(fdt, node, "bias-pull-up", NULL) != NULL) { 90 pull = GPIO_PULL_UP; 91 } else if (fdt_getprop(fdt, node, "bias-pull-down", NULL) != NULL) { 92 pull = GPIO_PULL_DOWN; 93 } else { 94 VERBOSE("No bias configured in node %d\n", node); 95 } 96 97 for (i = 0U; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 98 uint32_t pincfg; 99 uint32_t bank; 100 uint32_t pin; 101 uint32_t mode; 102 uint32_t alternate = GPIO_ALTERNATE_(0); 103 int bank_node; 104 int clk; 105 106 pincfg = fdt32_to_cpu(*cuint); 107 cuint++; 108 109 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 110 111 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 112 113 mode = pincfg & DT_GPIO_MODE_MASK; 114 115 switch (mode) { 116 case 0: 117 mode = GPIO_MODE_INPUT; 118 break; 119 case 1 ... 16: 120 alternate = mode - 1U; 121 mode = GPIO_MODE_ALTERNATE; 122 break; 123 case 17: 124 mode = GPIO_MODE_ANALOG; 125 break; 126 default: 127 mode = GPIO_MODE_OUTPUT; 128 break; 129 } 130 131 if (fdt_getprop(fdt, node, "drive-open-drain", NULL) != NULL) { 132 mode |= GPIO_OPEN_DRAIN; 133 } 134 135 bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node); 136 if (bank_node == 0) { 137 ERROR("PINCTRL inconsistent in DT\n"); 138 panic(); 139 } 140 141 clk = fdt_get_clock_id(bank_node); 142 if (clk < 0) { 143 return -FDT_ERR_NOTFOUND; 144 } 145 146 /* Platform knows the clock: assert it is okay */ 147 assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank)); 148 149 set_gpio(bank, pin, mode, speed, pull, alternate, status); 150 } 151 152 return 0; 153 } 154 155 /******************************************************************************* 156 * This function gets the pin settings from DT information. 157 * When analyze and parsing is done, set the GPIO registers. 158 * Returns 0 on success and a negative FDT/ERRNO error code on failure. 159 ******************************************************************************/ 160 int dt_set_pinctrl_config(int node) 161 { 162 const fdt32_t *cuint; 163 int lenp = 0; 164 uint32_t i; 165 uint8_t status; 166 void *fdt; 167 168 if (fdt_get_address(&fdt) == 0) { 169 return -FDT_ERR_NOTFOUND; 170 } 171 172 status = fdt_get_status(node); 173 if (status == DT_DISABLED) { 174 return -FDT_ERR_NOTFOUND; 175 } 176 177 cuint = fdt_getprop(fdt, node, "pinctrl-0", &lenp); 178 if (cuint == NULL) { 179 return -FDT_ERR_NOTFOUND; 180 } 181 182 for (i = 0; i < ((uint32_t)lenp / 4U); i++) { 183 int p_node, p_subnode; 184 185 p_node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 186 if (p_node < 0) { 187 return -FDT_ERR_NOTFOUND; 188 } 189 190 fdt_for_each_subnode(p_subnode, fdt, p_node) { 191 int ret = dt_set_gpio_config(fdt, p_subnode, status); 192 193 if (ret < 0) { 194 return ret; 195 } 196 } 197 198 cuint++; 199 } 200 201 return 0; 202 } 203 204 void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed, 205 uint32_t pull, uint32_t alternate, uint8_t status) 206 { 207 uintptr_t base = stm32_get_gpio_bank_base(bank); 208 unsigned long clock = stm32_get_gpio_bank_clock(bank); 209 210 assert(pin <= GPIO_PIN_MAX); 211 212 clk_enable(clock); 213 214 mmio_clrbits_32(base + GPIO_MODE_OFFSET, 215 ((uint32_t)GPIO_MODE_MASK << (pin << 1))); 216 mmio_setbits_32(base + GPIO_MODE_OFFSET, 217 (mode & ~GPIO_OPEN_DRAIN) << (pin << 1)); 218 219 if ((mode & GPIO_OPEN_DRAIN) != 0U) { 220 mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); 221 } else { 222 mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); 223 } 224 225 mmio_clrbits_32(base + GPIO_SPEED_OFFSET, 226 ((uint32_t)GPIO_SPEED_MASK << (pin << 1))); 227 mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1)); 228 229 mmio_clrbits_32(base + GPIO_PUPD_OFFSET, 230 ((uint32_t)GPIO_PULL_MASK << (pin << 1))); 231 mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1)); 232 233 if (pin < GPIO_ALT_LOWER_LIMIT) { 234 mmio_clrbits_32(base + GPIO_AFRL_OFFSET, 235 ((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2))); 236 mmio_setbits_32(base + GPIO_AFRL_OFFSET, 237 alternate << (pin << 2)); 238 } else { 239 mmio_clrbits_32(base + GPIO_AFRH_OFFSET, 240 ((uint32_t)GPIO_ALTERNATE_MASK << 241 ((pin - GPIO_ALT_LOWER_LIMIT) << 2))); 242 mmio_setbits_32(base + GPIO_AFRH_OFFSET, 243 alternate << ((pin - GPIO_ALT_LOWER_LIMIT) << 244 2)); 245 } 246 247 VERBOSE("GPIO %u mode set to 0x%x\n", bank, 248 mmio_read_32(base + GPIO_MODE_OFFSET)); 249 VERBOSE("GPIO %u speed set to 0x%x\n", bank, 250 mmio_read_32(base + GPIO_SPEED_OFFSET)); 251 VERBOSE("GPIO %u mode pull to 0x%x\n", bank, 252 mmio_read_32(base + GPIO_PUPD_OFFSET)); 253 VERBOSE("GPIO %u mode alternate low to 0x%x\n", bank, 254 mmio_read_32(base + GPIO_AFRL_OFFSET)); 255 VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank, 256 mmio_read_32(base + GPIO_AFRH_OFFSET)); 257 258 clk_disable(clock); 259 260 if (status == DT_SECURE) { 261 stm32mp_register_secure_gpio(bank, pin); 262 set_gpio_secure_cfg(bank, pin, true); 263 264 } else { 265 stm32mp_register_non_secure_gpio(bank, pin); 266 set_gpio_secure_cfg(bank, pin, false); 267 } 268 } 269 270 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure) 271 { 272 uintptr_t base = stm32_get_gpio_bank_base(bank); 273 unsigned long clock = stm32_get_gpio_bank_clock(bank); 274 275 assert(pin <= GPIO_PIN_MAX); 276 277 clk_enable(clock); 278 279 if (secure) { 280 mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); 281 } else { 282 mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); 283 } 284 285 clk_disable(clock); 286 } 287 288 void set_gpio_reset_cfg(uint32_t bank, uint32_t pin) 289 { 290 set_gpio(bank, pin, GPIO_MODE_ANALOG, GPIO_SPEED_LOW, 291 GPIO_NO_PULL, GPIO_ALTERNATE_(0), DT_DISABLED); 292 set_gpio_secure_cfg(bank, pin, stm32_gpio_is_secure_at_reset(bank)); 293 } 294